Contents Index Section 2


1.0 Introduction

This manual provides a comprehensive description of the AMSTRAD PC1512 hardware and firmware. General information about the PC1512, GEM Desktop and the delivered operating system software is contained in the AMSTRAD PC USER MANUAL. This manual is intended to satisfy the needs of advanced developers who must have access to the various resources available within the PC1512.

1.1 Central Processing Unit (CPU)

The CPU is an 8086-2 microprocessor with 1 Megabyte memory addressing capability (See Figure 1.1) running at a clock frequency of 8MHz. The CPU is connected to an on-board 16-bit system memory bus requiring four 125nS timing cycles (T-States) per access resulting in a 500nS memory cycle for 16-bit memory. The CPU is also connected on an on-board 8 bit I/O and memory peripheral bus with a 4 MHz clock, which in turn connects to an external (off-board) expansion bus. Operations on the 8-bit bus automatically incur 125nS wait states as follows:

OperationWait StatesBus Cycle
8-bit (Memory) 4 1.0 μS
16 to 8-bit convert (Memory)122.0 μS
8-bit (I/O) 6 1.25 μS
16 to 8-bit convert (I/O) 162.5 μS

The CPU is configured to run in maximum mode and the instruction set may be optionally extended by the addition of an 8087-2 Numeric Data Coprocessor. The 8087 BUSY output is connected directly to the 8086 NOT TEST input.


The main board memory consists of 512K bytes of system RAM with parity checking and 16K bytes of system ROM without parity checking. Note that all address constants in this document are in hexadecimal form except as noted.

The 512K byte user RAM starts at CPU memory address 00000 and extends to 7FFFF. An additional 128K bytes may be added externally in 32K byte blocks in the address space from 80000 to 9FFFF to extend the total system RAM to 640K bytes, provided the 640K byte option is not already installed on-board.

The 128K byte address space from A0000 to BFFFF is reserved for the 8-bit memory associated with certain controllers, and is not used by CPU programs. The on-board Alpha/Graphics VDU controller uses the 16K byte address range from B8000 to BBFFF for screen refresh memory. Also an optional external monochrome alphanumeric VDU controller uses the 4K memory address range from B0000 to B0FFF.

The 192K byte address space from C0000 to EFFFF is reserved for external expansion ROM address space. The optional Hard Disk controller uses the 20K byte address range from C8000 to CBFFF.

The 16K byte system ROM is at FC000 to FFFFF and contains the Resident Operating System (ROS) firmware. The 48K byte address range from F0000 to FBFFF is reserved for ROM space expansion.





    9FFFF 128K BYTES

[Figure 1.2]


The interfaces on the main board occupy the 8086 I/O addresses as follows:

000 - 00F8237 DMA Controller8237 DMA Controller
010 - 01FDo Not UseDo Not Use
020 - 0218259 Interrupt control8259 Interrupt control
022 - 03FDo Not UseDo Not Use
040 - 0428253 PIT Load Count (0-2)8253 PIT Read Count (0-2)
043 8253 PIT Load ModeUndefined
044 - 05FDo Not UseDo Not Use
060 No EffectPort A - Keyboard Code or System Status 1
061 Port B - System ControlPort B - (Readback)
062 No EffectPort C - System Status-2
063 No EffectDo Not Use
064 Write System Status-1Do Not Use
065 Write System Status-2Do Not Use
066 System ResetDo Not Use
067 - 06FDo Not UseDo Not Use
070146818 RTC AddressDo Not Use
071146818 RTC Data146818 RTC Data
072 - 077Do Not UseDo Not Use
078Clear Mouse X-CoordinateMouse X-Coordinate
079Do Not UseDo Not Use
07AClear Mouse Y-CoordinateMouse Y-Coordinate
07B - 07FDo Not UseDo Not Use
080Do Not UseDo Not Use
081DMA Page Register Ch 2Do Not Use
082DMA Page Register Ch 3Do Not Use
083DMA Page Register Ch 0,1Do Not Use
084 - 09FDo Not UseDo Not Use
0A0NMI Mask ControlDo Not Use
0A1 - 0BFDo Not UseDo Not Use
378Printer Data LatchPrinter Data Latch
379Do Not UsePrinter Status
37APrinter Control LatchPrinter Control Latch
37B - 37FDo Not UseDo Not Use
3D0CRTC Address RegisterDo Not Use
3D2 - 3D7Do Not UseDo Not Use
3D8VDU Mode ControlDo Not Use
3D9VDU Colour SelectDo Not Use
3DADo Not UseVDU Status
3DBClear Light Pen LatchDo Not Use
3DCSet Light Pen LatchDo Not Use
3DDVDU Colour Plane WriteDo Not Use
3DEVDU Colour Plane ReadDo Not Use
3DFVDU Graphics Mode 2 BorderReserved
3F0 - 3F1Do Not UseDo Not Use
3F2Drive SelectionDo Not Use
3F3Do Not UseDo Not Use
3F4Do Not Use765 FDC Status
3F5765 FDC Data765 FDC Data
3F6 - 3F7Do Not UseDo Not Use
3F8 - 3FF8250 UART Tx Data/Control8250 UART Rx Data/Control

Note: I/O addresses above 3FF, if accessed, wrap around and are mapped onto the range 000-3FF. Any of the unlisted addresses may be used in the future.


The 8086 CPU I/O addresses on the expansion bus are as follows:

200 - 20FExternal Game Control Interface
210 - 217External Bus Expansion Unit
278 - 27FExternal Printer Port
2B0 - 2DFExternal Secondary Enhanced Graphics Controller
2F8 - 2FFExternal Asynchronous Serial RS232C Port
300 - 31FExternal Prototyping Card
320 - 32FExternal Hard Disk Controller
380 - 38CExternal SDLC Serial RS232C Port or Extended BSC Controller
390 - 393External Cluster Controller
3B0 - 3BBExternal Monochrome VDU Controller
3BC - 3BFPrinter Port
3C0 - 3CFExternal Graphics Controller

I/O Addresses wrap around above 3FF occurs as described on page 10.

External cluster controllers at 790-793, B90-B93, 1390-1398 and 2390-2393 wrap around to I/O addresses 390-393

1.5 Direct Memory Access (DMA)

The AMSTRAD PC supports four DMA channels on the system board, using an 8237-4 DMA controller and programmable page registers to extend its addressing range from 64k bytes to 1M bytes. Each channel is able to transfer data in blocks of up to 64K bytes within a page. The DMA channels are for 8-bit data transfers between (8-bit) I/O devices and 8-bit or 16-bit memory.

In peripheral (slave) mode, CPU I/O address lines A0 - A3 are connected conventionally so that 16 command codes appear in the order described in the 8237 data sheets (See section 3.5).

The DMA controller CLK is driven at 4MHz (± 0.1%). In master mode during DMA transfers on channels 1,2 and 3, one wait state is added resulting in a five-clock DMA bus cycle of 1.25uS. Channel 0 transfers have a four-clock bus cycle of 1uS.

The DMA channel request signals are as follows:

DMA ChannelUSE
08253 Timer/Counter OUT1 output - for memory refresh.
1Spare for use by expansion bus. Used by external SDLC Serial Port.
2765 Floppy Disk Controller DRQ output. Available on the expansion bus.
3Spare for use by expansion bus. Used by external Hard Disk Controller.

1.5.1 DMA Page Registers

DMA channels 1, 2 and 3 can address the entire 1M byte addressing range of the 8086 CPU through the use of their associated DMA page registers. There are three DMA registers, one each for channels 1 through 3. Each page register defines for its channel which one of sixteen 64K byte pages in the 1M byte address range DMA transfers are to occur. The page registers are static so that modulo 64K byte addressing occurs at page boundaries. They are located in the I/O address space in the range 081-083.

The DMA page register bit assignments are as follows:

BitOutput Use
7Not Connected
6Not Connected
5Not Connected
4Not Connected
3Address bit A19
2Address bit A18
1Address bit A17
0Address bit A16

1.5.1 DMA Initialisation

Following a reset, system initialisation firmware (in the ROS) sets up the 8237 for channel 0 (dynamic refresh) operation as follows:

FunctionInitialised State
Word Count64K Transfers
Single Mode
Disable Memory to Memory
Enable Controller
Normal Timing
Fixed Priority
Late Write
DREQ Active High
DACK Active Low
Clear Channel 0 Mask Bit

After power-up or system reset the DMA page registers are undefined and are initialised to zero by the ROS firmware and all 8237 internal locations for channels 1-3 are initialised to a state comparable to the channel zero initialisation above.

Following industry compatibility, memory to memory DMA is not supported on the PC1512. It is prohibited due to timing considerations.

1.6 System Interrupts

Nine levels of hardware interrupt are provided for in the system by the CPU Non Maskable Interrupt (NMI) and by an 8259A-2 Interrupt Controller. All levels including NMI, are maskable under software control.

CPU I/O address line A0 is connected conventionally so that the command codes appear in the order described in the 8259 data sheets. The SP/EN pin is tied high signifying that the device is to be hardware un-buffered and designated as a master, not a slave.

1.6.1 Interrupt Levels

The interrupt levels are assigned as follows:

LevelAssigned Function
NMIMemory Parity Error and 8087 NDP INT output.
08253 Timer/Counter Out0 output.
1Keyboard Scan Code Receiver.
2146818 Real Time Clock IRQ output.
Available on expansion bus.
May be used by Enhanced Graphics Adapter
3Spare for use by expansion bus.
Used by external (secondary) Asynchronous Serial Port and external SDLC Serial Port.
48250 UART INTRPT output.
Available on expansion bus.
Used by external SDLC Serial Port.
5Spare for use by expansion bus. Used by external Hard Disk Controller.
6765 Floppy Disk Controller INT output.
Available on the expansion bus.
7Parallel Printer Port.
Available on the expansion bus.
Used by external Printer Port (secondary) Printer Port (tertiary), external Monochrome VDU Controller, and external cluster controllers.

1.6.2 Interrupt Controller Initialisation

Following a reset, the initialisation firmware in the ROS sets the 8259 Interrupt Controller to operate as follows:

8086 system,
Single (not cascaded),
Normal fully nested (not special),
Buffered mode - slave,
Normal EOI (not auto),
Fixed priority - level 0 highest, level 7 lowest.

1.6.3 NMI Mask Control

The NMI Mask Control is a write only register at I/O address 0A0 and allows the CPU non-maskable interrupt (NMI) input to be enabled or disabled by software. The Bit assignments are as follows:

BitOutput Use
7Enable NMI.
6 - 0Not Connected

Following a reset NMI is disabled.

NMI can be connected to the 8087 NDP, the on-board memory parity check circuit, and the expansion bus I/OCHCK (I/O Channel Check).

1.7 Programmable Interval Timers

Three programmable timer/counters are provided at I/O Addresses 040 - 043 by an 8253 Programmable Interval Timer (PIT) device. They are defined as follows:

0General Purpose Timer.
1Used by DMA channel 0 (for dynamic ram refresh).
2Tone Generation for Speaker.

1.7.1 Timer Configuration

The 8253 timers are configured as follows:

CLK 0,1,21.193 MHz (± 0.1%)
GATE 0,1Always 'ON'.
GATE 2Controlled via Port B (System Control Channel) Speaker Modulate output.
OUT 0Interrupts on 8259 PIC IR0 input.
OUT 1Requests on 8237 DMA DREQ0 input.
OUT 2Logical 'AND' with Port B (System Control Channel) Speaker Drive output. Also goes to Port C (System Status-2 Channel) as an input.

1.7.2 Counter 1 initialisation

Following a reset, the system initialisation firmware in the ROS programs the 8253 PIT for counter 1 (dynamic ram refresh) operation as a rate generator producing a signal with a period of 15.13 uS. There are no restrictions requiring the initialisation and programming of counters 0 and 2.

1.8 System Status and Control

Two system status input channels and four output channels are provided on-board. Ports A, B and C emulate a pre-programmed 8255 PPI device. They are located in the I/O address space in the range 060 - 06F. Port B is programmed for control output, Port A is programmed either for Status-1 input or for receiving data from the keyboard, and Port C is programmed for Status-2 input.

Ports A, B and C emulate an 8255 PPI that has been set up as follows:

Group A Mode 0,Group B Mode 0,
Port A = input,Port B = output,
Port C(U) = input.Port C(L) = input.

Unlike an 8255, power-up and reset do not affect this configuration.

1.8.1 Port B - System Control

The System Control channel is located at I/O Address 061. Its bit assignment is as follows:

Bit (PBn)Output Use
7Enable Status-1/Disable Keyboard Code on Port A.
6Enable incoming Keyboard Clock.
5Prevent external parity errors from causing NMI.
4Disable parity checking of on-board system Ram.
3Undefined (Not Connected).
2Enable Port C LSB / Disable MSB. (See 1.8.3)
1Speaker Drive.
08253 GATE 2 (Speaker Modulate).

When bit 7 is set high (1), Status-1 data is enabled on Port A, the keyboard data path and keyboard interrupts are disabled. When bit 7 is set low (0), keyboard input data is enabled on port A, the keyboard data path and keyboard interrupts are enabled.

The keyboard interface operates as follows: Each incoming keycode is latched on-board, causing a keyboard interrupt (on level 1). While the interrupt remains pending, the incoming keyboard data signal is forced low as an acknowledgement to the keyboard that the keycode has been received. As soon as the interrupt has been cleared, the keyboard may use the Data signal to transmit the next keycode.

PB1 may be toggled to drive the speaker with a corresponding pulse train. The speaker may also be driven by a wave form from the 8253 PIT OUT2 output (simultaneously with PB1, if required).

PB0 may be toggled to drive the 8253 gate input, hence modulate counter 2 operations and therefore the speaker with a corresponding waveform. Thus there are three different methods of driving the speaker which may all be performed simultaneously to create various audio effects.

1.8.2 Port A - Status-1 Input/Keyboard Code

Port A is a read only location located at I/O Address 060. When PB7 is set to high (1) reading Port A loads Status-1. When PB7 is set low (0) reading Port A loads keyboard data. The bit assignments for port A are as follows:

Bit (PAn)Status-1Keyboard Input
7Always 0. KBD7
6Second Floppy disk drive installed.KBD6
5DDM1 - Default Display Mode bit 1.KBD5
4DDM0 - Default Display Mode bit 0.KBD4
3Always 1.KBD3
2Always 1.KBD2
18087 NDP installed.KBD1
0Always 1. KBD0

The Default Display Mode bits (DDM1, DDM0) are set up by the ROS during system initialisation based on Non-Volatile Ram (NVR) selections as follows:

01 (1)
Colour, alpha, 40 X 25 chars, bright white on black.
10 (2)
Colour, alpha, 80 X 25 chars, bright white on black.
11 (3)
External Monochrome controller, 80 X 25 chars.

Following a reset, the hardware selects VDU mode 2. The ROS then sets the initial VDU state based on the DDM value.

1.8.3 Port C - Status-2 Input

Port C is a read only location located at I/O Address 062. Its bit assignments are as follows:

Bit (PCn)Input Use
7On-board system RAM parity error.
6External parity error (I/OCHCK from expansion bus).
58253 PIT OUT2 output.
4 Undefined (Not Connected).
  LSB or MSB (depends on PB2)

PC7 is forced to the zero state when on-board system RAM parity checking is disabled by PB4.

When the I/OCHCK condition (external parity error) from the expansion bus is disabled from causing NMI (by PB5 set high), PC6 reflects the state of the I/OCHCK input else it reflects the latched state of I/OCHCK.

The value of RAM4-RAM0 denotes the amount of system RAM fitted to the system as follows:

01110512K bytes on-board.
01111544K bytes (32K external).
10000576K bytes (64K external).
10001608K bytes (96K external).
10010640K bytes (128K external or fitted on-board).

1.8.4 Write System Status-1

The Write System Status-1 register is a write only register at I/O Address 064 and is initialised by the Resident Operating System (ROS) firmware based on values obtained from the Non-Volatile Ram (NVR). It is used in conjunction with the 8255 PPI Port A emulation. The bit assignments are as follows:

BitOutput Use
7No effect.
6PA6 - Second Floppy disk drive installed.
5PA5 - DDM1.
4PA4 - DDM0.
3No effect.
2No effect.
1PA1 - 8087 NDP installed.
0No effect.

1.8.5 Write System Status-2

The Write System Status-2 register is a write only register at I/O Address 065 and is initialised by the Resident Operating System (ROS) firmware based on values obtained from the Non-Volatile Ram (NVR). It is used in conjunction with the 8255 PPI Port C emulation. The bit assignments are as follows:

BitOutput Use
7PC2 (MSB) - Undefined.
6PC1 (MSB) - Undefined.
5PC0 (MSB) - Undefined.
4PC3 (MSB) - RAM4.
3PC3 (LSB) - RAM3.
2PC2 (LSB) - RAM2.
1PC1 (LSB) - RAM1.
0PC0 (LSB) - RAM0.

1.8.6 System Reset

Any write access to I/O Address 066 regardless of the value written will cause the hardware to generate an immediate 512uS system reset and pulse the reset line on the expansion bus. The contents of the on-board system RAM is preserved following a system reset.

1.9 Real Time Clock

HD146818 Real Time Clock plus RAM device is installed and backed up by a set of four non-rechargable size AA batteries. The clock device provides a time of day clock with alarm, a one hundred year calendar, a programmable periodic interrupt, and 50 bytes of static RAM. The static RAM is called the Non-Volatile RAM (NVR) and used to store system configuration data such as number of disk drives, memory size, serial I/O parameters, and default VDU screen mode. The ROS firmware maintains a checksum of the NVR and will reset the configuration data to "sensible values" during startup whenever the checksum value is incorrect (thus destroying your actual configuration). Even though direct hardware access to the NVR is possible it is recommended that the programs make use of the ROS Enhanced Function Interrupt (Interrupt 21) to access the NVR because these properly maintain the NVR checksum value.

When system power is off and the 146818 is on battery backup power, the functions which remain active are the clock and the retention of RAM data. No battery power is used while the system power is on.

The input crystal oscillator runs at 32.768 KHz.

The 146818 interrupt request is connected to the 8259 system interrupt controller on level 2 (which is also available on the expansion bus). The 146818 power-sense input PS is connected to a battery condition sensor. When the backup battery voltage is sufficiently low, the VRT bit in register D becomes set indicating that the time, the calendar and the NVR data are no longer valid. When this condition is noted during startup, the firmware outputs the message "Please fit new batteries" and resets the NVR to default values (See section 2.4).

All the features described in the 146818 data sheet are available with the exceptions that the CKOUT (clock output) and SQW (square wave output) pins are not connected on the main board.

Writing or reading the NVR involves a two step sequence for each byte that is accessed. The RTC Address channel (I/O Address 070) is first loaded with the NVR location to be accessed. Then the RTC Data channel (I/O Address 071) is either written or read to complete the I/O operation. This facility should be used with caution in order to avoid disturbing the system configuration data.

1.10 Parallel Printer Port

The printer port provides an interface for driving 8-bit and 7-bit Centronics compatible printers. The timing of the signals to the printer is under direct software control. There is a read/write control latch for sending control signals to the printer, an unlatched read-only printer status channel, and a read/write data latch for sending printer data.

1.10.1 Printer Data Latch

The printer data latch is a read/write record at I/O address 378 and its layout is as follows:

Bit (Dn)Output/Input UseCable Polarity
7Data 7Hi
6Data 6Hi
5Data 5Hi
4Data 4Hi
3Data 3Hi
2Data 2Hi
1Data 1Hi
0Data 0Hi

The contents of the data latch are undefined following a power-up or system reset.

1.10.2 Printer Control Latch

The printer control latch is a read/write record at I/O address 37A and its layout is as follows:

BitOutput/Input UseReset StateCable Polarity
7-5No effect 
4Enable Int on ACKFalse
3Select PrinterFalse
2Reset PrinterTrue
1Select Auto FeedFalse
0Data StrobeFalse

When Interrupt on ACK is enabled an incoming Printer Acknowledge condition will cause a system interrupt on level 7 (which is also available on the expansion bus).

If the printer control lines normally driven via latched bits D0 - D3 are driven externally, the data read on input to this channel will be the logical OR of the latched bits and the externally driven bits, e.g. If a data bit is false and the corresponding cable bit is driven true by the external driver, the bit input will be true.

Following power-up or system reset, the control latch contents assume reset conditions as shown.

Note that this is a general purpose printer interface and that not all printers require all the control signals, hence the provision for non-standard printers to be able to drive some of the control signals as inputs to the main board. The timing requirements on Centronics compatible printers generally specify that data must be present at 1uS before the strobe is made active, and must remain valid for at least 1uS after strobe goes inactive. The strobe duration must be between 1uS and 500 uS. Printer Busy status can be inspected as soon as the strobe is inactive in order to determine when more data can be sent.

1.10.3 Printer Status Channel

The Printer Status Channel is a read only register at I/O Address 379 (hex). Its layout is as follows:

BitInput UseCable Polarity
7Printer BusyHi
6Printer AcknowledgeLo
5Paper OutHi
4Printer SelectedHi
3Printer ErrorLo
2LK3 fitted 
1LK2 fitted 
0LK1 fitted 

LK1 - LK3 are general purpose factory installed option links on the main board which are used by the firmware to distinguish different machine configurations. The first seven states (0 - 6) are used for language variants and the all ones (7) state is used for Power-Up Self Test Maintenance Mode (See section section 2.2).

Note that this is a general purpose printer interface and that not all printers implement all the status lines, nor do they all attach the same meanings to the error conditions.

Printer Busy normally indicates that a printer cannot receive data, for example during data entry, printing, when offline, or during a printer error condition.

Printer Acknowledge, if implemented is generally asserted by a printer to indicate that data has been received and the printer is ready to receive the next data. Note that Printer Acknowledge (ACK) can also be set to cause interrupts (See 1.10.2).

Section 1.14 contains the printer connector pin assignments.

1.11 Alpha/Graphics Colour VDU Controller

The VDU controller is implemented as a partially emulated MC6845 CRTC and provides either a colour alphanumeric display (Alpha) or a colour pixel display (Graphics). The frame rate is 60 Hz non-interlaced and 200 scan lines are displayed between the top and the bottom borders. The highest resolution on a scan line between the left and the right borders is 640 pixels displayed.

The 16K Byte VDU screen memory area (from B8000 to BBFFF) is overlaid (in Graphics modes) in four planes giving a resultant 64K bytes of display RAM and enabling sixteen colours to be available.

The sixteen colours available on the display are as follows:

RedGreenBlueIntensityLuminance Colour
00119Light Blue
010112Light Green
011113Light Cyan
100110Light Red
101111Light Magenta
111115Intense White

The "Light" colours imply higher intensity video.

On the monochrome monitor the R,G,B and I signals are summed and weighted 2, 4, 1 and 8 respectively to form the 16 level grey scale luminance column in the table.

1.11.1 Alpha Display

Two Alpha modes are available: either (medium resolution) 40 characters by 25 rows or (high resolution) 80 characters by 25 rows. The modes require 2000 bytes or 4000 bytes of display RAM respectively. A low resolution 160 by 100 pixels 16 colour graphics mode may be obtained in high resolution Alpha mode by programming the CRTC for two scan lines per character, and by using certain half-block characters in the character set as pixels. This mode requires 16000 bytes of display RAM.

The character set is formed by a ROM character generator and each of the 256 characters is made up of a 8 by 8 pixel matrix. Each character displayed takes up two bytes of display RAM consisting of a character code byte and an associated attribute byte. The attribute byte allows a choice of either 16 foreground and 8 background colours per character, plus blinking, or a choice of 16 colours for both foreground and background without blinking. The display border may be any one of 16 colours.

The display starting address in the display RAM is programmed via the CRTC. The starting address must be on an even address boundary and it addresses the first (leftmost) character position in the top row of the display. In each pair of display RAM bytes, the even address is for the character code and the odd address is for the attribute byte. Subsequent characters are displayed along the row from left to right. When the end of a row is reached the next pair in the display RAM appears in the first character position of the next row down.

The attribute byte for each is as follows:

Bit (ATn)Definition
7Intensity (Background) or Enable Blink (depends on Mode Control Bit 5)
6Red (Background)
5Green (Background)
4Blue (Background)
3Intensity (Foreground)
2Red (Foreground)
1Green (Foreground)
0Blue (Foreground)

1.11.2 Graphics Display

There are two Graphics modes available, either Mode 1 (medium resolution) 320 pixels per scan line with a choice of four colours per pixel or Mode 2 (high resolution) 640 pixels per scan line with a choice of sixteen colours per pixel. The modes require 16000 and 64000 bytes of display RAM respectively.

The display RAM is divided into four 16K byte planes, one each for all the Red, Green, Blue and Intensity bits. Each plane may be individually written or read by the CPU, and two or more planes may be selected by the CPU for writing simultaneously with the same data. Graphics Mode 1

The colour planes are not used in Mode 1, since only 16K bytes of display RAM (i.e. one plane) is ever required. For this reason system reset or entry into any other display mode other than graphics mode 2 forces selection of all planes for simultaneous writing by the CPU, which appears (to the software) as though only one 16K byte display RAM is installed in the address range from B8000 to BBFFF.

In Mode 1, the display memory for one scan line (320 pixels) consists of 80 bytes. Each pixel requires two bits such that four pixels are specified by each byte. The leftmost pixel is contained in the two MS bits of the byte and the two bit pairs for the remaining pixels follow on logically in left to right fashion. The two bit field for each pixel specifies one of four colours in one of three palettes (See 1.11.3 - VDU Control Registers). The three palettes are as follows:

B1B0Palette 0Palette 1Palette 2

In Mode 1 the 100 even scan lines (0, 2, 4, ... 198) are contained in the graphics memory space from B8000 to B9F3F and the 100 odd scan lines (1, 3, 5, ... 199) are contained in the memory address range from BA000 to BBF3F. The graphics memory appears as follows:

 <-- 320 Pixels (2 Bits Per) --> 
B8000Scan Line 0 (80 Bytes)B804F
B8050Scan Line 2B809F
B80A0Scan Line 4B80EF
B9EF0Scan Line 198B9F3F
BA000Scan Line 1BA04F
BA050Scan Line 3BA09F
BA0A0Scan Line 5BA0EF
BBEF0Scan Line 198BBF3F

The layout of a byte of graphics RAM in Mode 1 is as follows:

RAM Bit: 7:6 5:4 3:2 1:0
Pixel: 0 1 2 3
PIXEL Bit: B1 : B0 B1 : B0 B1 : B0 B1 : B0 Graphics Mode 2

In Mode 2 the four memory planes become active and the colour of each pixel is controlled by the setting of the VDU Colour Plane Write Register at the time a pixel is written. The display memory for one scan line consists of 80 bytes, each containing 8 pixels. Since there are four planes, each displayed pixel is actually made up from 4 bits of information (R,G,B,I) specifying one of 16 colours. The border is programmable to any one of the 16 colours.

The ROS emulates two colour 640 by 200 graphics mode (software mode 6) by writing to all four colour planes (Intense White). Then the VDU Colour Plane Select register is used as the foreground palette selector. See section 2.3.7.

The layout of a byte of graphics RAM in Mode 2 is as follows:

RAM Bit: 7 6 5 4 3 2 1 0
Pixel: 0 1 2 3 4 5 6 7

The address mapping of the scan lines in display RAM for mode 2 is identical to that depicted for display Mode 1 - all even scan lines (from B8000 to B9F3F) followed by all odd scan lines (from BA000 to BBF3F). The major difference is that data written to one location may actually be stored in up to four planes simultaneously.

Note that even though the same physical address range is used between graphics and text modes, the internal data storage within VDU RAM changes between the different modes. This means that data patterns stored in successive locations in text modes will be found in the IRGB planes when graphics mode 2 is selected. Also data patterns stored in graphics mode 1 will be found on all planes when graphics mode 2 is selected. It is therefore not generally an acceptable practice to store information in one VDU mode and then switch to another mode else unexpected results may be encountered.

1.11.3 VDU Control Registers

There are five programmable registers for VDU mode and colour selection. These consist of the VDU Mode Control Register, the VDU Colour Select Register, the VDU Colour Plane Write Register, the VDU Colour Plane Read Register, and the VDU Graphics Mode 2 Border Register.

On power-up or following a system reset, the control registers are preset as described below. VDU Control Registers

The VDU Mode Control Register is a write only register located at I/O address 3D8. It is used to control the state of the VDU circuitry, selecting Alpha or Graphics mode and the various sub options available within Alpha and Graphics modes.

The layout of the VDU Mode control register is as follows:

BitOutput Use
7No effect
6No effect
5Enable Blinking Chars (disable intensified backgrounds)
4Select Graphics Mode 2 (de-select graphics mode 1)
3Enable Video Display
2Select Palette 2 (de-select palettes 0,1)
1Select Graphics modes (de-select Alpha modes)
0Select Alpha 80 Char mode (de-select 40 Char mode)

When bit 5 is set in Alpha modes, the foreground of all displayed characters with attribute bit 7 (AT7) set will blink at 1.875 Hz (1/32 frame rate) in synchronism with frame flyback. Bit 5 has no effect in Graphics modes.

Bit 4 (Select Graphics Mode 2) has no effect in Alpha modes.

The Select Palette 2 bit (bit 2) has no effect in Alpha modes or in Graphics mode 2. It is used in conjunction with bit 5 of the VDU colour select register to control graphics mode 1 palette. To select palette 2, bit 5 of the VDU colour select register must be reset and bit 2 of the VDU mode control register must be set.

Bit 0 (Select Alpha 80 Char mode) has no effect in Graphics modes.

To avoid unsightly effects on the screen, this register should be updated during frame flyback time. Any kind of mode changing should preferably be done with video disabled. Mode changing involves the use of bits 1 and 0 and usually some re-programming of the CRTC.

On power-up and following a system reset, all bits of this register are cleared to zero. VDU Colour Select Register

The VDU Colour Select Register is a write only register located at I/O address 3D9 and is used for controlling border colour in alpha modes and for selecting palette, border and pixel colour options in the graphics modes. The layout of the VDU Colour select register is as follows:

BitAlpha ModesGraphics Mode 1Graphics Mode 2
7,6No EffectNo EffectNo effect
5No EffectSelect Palette 1 (Deselect palette 0)No effect
4No EffectForeground Intensity for palettes 0, 1 & 2No effect
3Intensity (Border)Intensity (Backgnd and Border)Intensity (Pixel)
2Red (Border) Red (Background and Border)Red (Pixel)
1Green (Border)Green (Background and Border)Green (Pixel)
0Blue (Border) Blue (Background and Border)Blue (Pixel)

In Graphics mode 2, the display border colour is programmed via the VDU Graphics Mode 2 Border register. The ROS makes use of the VDU Colour Select register in VDU I/O software mode 6 as a palette selector by writing all graphics in bright white. The overall screen palette is then controlled by setting the VDU Select register (which is initialised to 07h by the ROS on selection of mode 6). This mode effectively emulates 2 colour 640 by 200 graphics mode using 16k bytes of VDU memory. (See section 2.3.7 - VDU I/O.)

When using the full 16 colour capability in Graphics mode 2, programmers must set the VDU Colour select register to 0Fh and vary the plane selection with the Colour Plane Write register.

To avoid unsightly effects on the screen this register should only be updated during frame flyback time.

On power-up or following a system reset, all bits in this register are cleared. VDU Colour Plane Write Register

The VDU Colour Plane Write Register is a write only register located at I/O address 3DD. It is used in Graphics Mode 2 for controlling which colour plane or combination of colour planes will be written to when addressing the display RAM (B8000 to BBFFF hex).

The bit assignments for the VDU Colour Plane Write register are as follows:

BitOutput Use
7 - 4No effect
3Allow CPU write to Intensity Plane
2Allow CPU write to Red Plane
1Allow CPU write to Green Plane
0Allow CPU write to Blue Plane

The CPU simultaneously writes the memory planes that are enabled for writing.

Writing to this register has no effect except in Graphics Mode 2.

Following the selection of Graphics Mode 2, (other than when already in Graphics Mode 2) bits 0 through 3 are set to one, but may subsequently changed by writing to this channel. VDU Colour Plane Read Register

The VDU Colour Plane Read Register is a write only register located at I/O address 3DE. It is used in Graphics Mode 2 for controlling the selection of which one of the four colour planes in the display RAM is to be read by the CPU when memory in the 16K byte address range from B8000 to BBFFF (hex) is read. The bit assignments for the VDU Colour Plane Read register are as follows:

BitOutput Use
7 - 2No effect
1Read Select bit 1 (RDSEL1)
0Read Select bit 0 (RDSEL0)

The CPU reads from whichever one of the four colour planes in display RAM is selected according to the RDSEL value as follows:

RDSELColour Plane Selected for CPU read
0Blue Plane
1Green Plane
2Red Plane
3Intensity Plane

Writing to this register has no effect except in Graphics Mode 2.

On power-up or following a system reset or selection of any other mode other than Graphics Mode 2 the register is cleared and fixed so that the CPU will only read from the Blue Plane. VDU Graphics Mode 2 Border Register

The VDU Graphics Mode 2 Border Register is a write only register located at I/O address 3DF. It is used in Graphics Mode 2 for specifying the border colour.

The bit assignments for the VDU Graphics Mode 2 Border register are as follows:

BitOutput Use
7 - 4No effect
3Border Intensity
2Border Red
1Border Green
0Border Blue

Bits 0 through 3 specify one of sixteen colours.

To avoid unsightly effects on the screen this register should only be updated during frame flyback time.

On power-up or following a system reset, or following selection of Graphics Mode 2 (other than when already in Graphics Mode 2) the register is cleared (Graphics Mode 2 border black).

1.11.4 VDU Status Register

The VDU Status Register is a read only register located at I/O address 3DA. It may be read at any time to determine the following:

BitInput Use
7 - 4Undefined
3Frame Flyback Time
2Light-pen switch off
1Light-pen latch set
0Toggle bit

Frame flyback time starts at the same time as the bottom border and lasts for 46 horizontal scan periods, ending 16 scans before the end of the subsequent top border.

Bit 2 reflects the state of the light-pen push button switch, which is neither latched nor debounced.

Bit 1 when set (1) indicates that the light pen latch is set, triggered either by a pulse from the light pen or by writing data to the light pen channel. Writing any data to the Clear Light Pen channel clears the latch, which is undefined following power-up and unaffected by system reset.

When the VDU Status Register is read, bit 0 toggles to the opposite state. Bit 0 is cleared (0) following power-up or following system reset.

1.11.5 MC6845 CRTC Emulation

The VDU controller is a partial emulation of a MC6845 CRT Controller device. Some of the registers which are programmable in an actual MC6845 are not programmable in the AMSTRAD PC1512. These differences are noted in the table which follows.

The remaining registers must be programmed according to the VDU mode of operation required in conjunction with the VDU Mode and Colour Select Registers previously described. A mode changing operation should be performed in the following sequence: Disable video, reprogram the CRTC as required, reprogram the Mode and Colour select registers as required, (maintaining video disabled), initialise display RAM as required, enable video.

The CRTC is controlled by way of two I/O addresses, the CRTC Address register and the CRTC Data I/O location. The CRTC Address register is a write only register located at I/O address 3D0 (and all even addresses to 3D6). The address register is a 5 bit register used to select one of eighteen internal control registers (R0 - R17). Addresses greater than 17 produce no results. Once the CRTC Address register has been loaded, the CRTC Data I/O location which is located at I/O 3D1 (and all odd addresses to 3D7) allows access to the selected internal CRTC register. Depending on the particular register selected the location may be either Read/Write (RW), Read Only (RO) or Write Only (WO).

The emulated MC6845 CRTC internal register layout and their initialised values are as follows:

Register Number Register Name Alpha 40 Char Mode Alpha 80 Char Mode Graphics Modes R/W Type
R0* Horizontal Total-------
R1 Horizontal Displayed[ 40 ][ 80 ][ 40 ]WO
R2* Horizontal Sync Posn.-------
R3* Horizontal Sync Width-------
R4* Vertical Total-------
R5* Vertical Total Adj.-------
R6 Vertical Displayed[ 25 ][ 25 ][ 100 ]WO
R7* Vertical Sync Posn.-------
R8* Interlace-------
R9 Max. Raster Address070701WO
R10 Cursor Start Raster060606WO
R11 Cursor End Raster070707WO
R12 Start Address (MS)000000WO
R13 Start Address (LS)000000WO
R14 Cursor Location (MS)000000RW
R15 Cursor Location (LS)000000RW
R16 Light Pen Posn. (MS)------RO
R17 Light Pen Posn. (LS)------RO

Note that all values above are in decimal format.

Registers marked '*' are not software programmable in the emulated MC6845 CRTC implementation, unlike a real MC6845. They are fixed in hardware according to the VDU mode currently selected.

The two sets of registers marked by '[ ]' should normally be programmed nonzero. The magnitude of the non-zero value will have no effect on the display, but a zero value in either register will cause the whole screen to display the border colour.

The cursor function of a 6845 CRTC is supported only in Alpha modes. The cursor blinking function is performed by a circuit external to the CRTC and blinks the cursor at 3.75Hz (1/16 frame rate) in synchronism with frame flyback. The cursor non-display feature, variable blink rate feature and variable blink period feature of the 6845 CRTC are not supported.

The valid range of values for Cursor Start Raster (R10) is from 0 to 30 (decimal) and the value of 31 (which will turn the cursor off). Values greater than 31 are not recommended.

The light pen function of a 6845 CRTC is supported:

Horizontal ResolutionVertical Resolution
Alpha Modes:1 Char column1 Char row
Graphics Modes:1 Pixel Word2 Scans (ie. 1 row)

If "M" = Current Display Address then in...

Graphics, LPEN value = M + 1 or M + 2.
Alpha 80, LPEN value = M + 3 or M + 4.
Alpha 40, LPEN value = M + 1 or M + 2.

1.11.6 CRTC Display Addressing

In Alpha modes, the CRTC register values for start address and light pen position are in the 8K range 0000h to 1FFFFh, and wraparound occurs above this range. The register value corresponding to a character position in display RAM must be derived from the even byte address in the 16K range B8000h to BBFFFh by subtracting B8000h and halving.

In Graphics modes, the CRTC register values for start address and light pen position are in the 4K range 000h to FFFh, and wraparound occurs above this range. A register value corresponds to two pairs of pixel bytes in display RAM on word boundaries, one pair displayed on an even scan and the other pair displayed on the following odd scan in the same horizontal position.

The register corresponding to the pixel byte pair position in display RAM must be derived from the even byte address in the 8K range B8000h to B9FFFh (for an even scan) by subtracting the address offset B8000h and halving. Similarly for the odd scan line the offset BA000h is subtracted from an even byte address in the range BA000h to BBFFFh and halved. Mode Mapping Relationships

There are important differences in the way the VDU Controller maps and uses the display RAM for different VDU display modes.

The Alpha Mode to Graphics Mode memory mapping follows the scheme depicted in fig 1.3.

The concept of planes does not exist in character modes and character data is stored sequentially in display RAM. In Graphics modes, the display RAM is viewed logically as colour planes which are grouped in four byte groups. This means that there is an effective "gear change" between alpha and graphics modes and storing in an address such as B8000h in graphics modes spans the address range from B8000 to B8003 in alpha modes.

In Graphics Mode 1, the display RAM mapping is the same as for Graphics Mode 2, but only the data contained on the Blue plane is used to form pixels on the screen. When the CPU writes to display RAM in Graphics Mode 1, the same data is stored in all planes.

It is very important to note that it is impossible to store character and attribute pairs in consecutive display RAM in graphics mode. Attempting to clear the text screen with text data while in graphics mode and then switching to an alpha display mode will produce a "Stars and Bars" effect on the screen.

[Figure 1.3] Display RAM Access Overhead

The VDU display timing and system CPU/DMA timing are derived from different, unrelated reference frequencies. For this reason CPU accesses to the display RAM must be synchronised to the display timing by the VDU controller, and this is done by inserting CPU wait states as appropriate.

Whenever the CPU accesses the display RAM, the total number of 125nS wait states incurred, including those already added automatically by the 8bit bus conversion process, will range from a minimum of 12 to a maximum of 46. At most, a situation in which 46 wait states are necessary could occur once every 63.7uS, in all modes. Similarly, the need for 38 wait states could occur at most every 63.7uS in Graphics mode 2 or in 80 x 25 Alpha mode. Alpha Mode Character Generator ROM

The 8K character generator ROM can contain a maximum of four different character sets, each in a different 2K byte quadrant of the ROM. Only one character set can be used at a time and it is selected by means of two option links, LK6 and LK7, located on the right hand side main board.

The character set selection is as follows:

LK7LK6Character Set Selected
OutOutROM Fourth Quadrant - Default factory setting.
InOutROM Third Quadrant - (optional Danish).
OutInROM Second Quadrant - (optional Danish).
InInROM First Quadrant - (optional Greek - late models).

Floppy Disk Controller

The floppy disk controller is based on the NEC uPD765A single chip controller, and supports one or two 5.25 inch single or double sided, MFM double density floppy disk drives with a data rate of 250 kilobits per second.

The FDC is controlled by way of the Drive Selection register (at I/O Address 3F2) and it is defined as follows:

Bit (Dn)Output Use
7 - 6No effect
5Switch motor(s) on and enable drive 1 selection
4Switch motor(s) on and enable drive 0 selection
3Allow 765A FDC to interrupt and request DMA
2765A reset
1Drive Select Bit 1 (DS1)
0Drive Select Bit 0 (DS0)

The Drive Select bits (DS1, DS0) are only valid for values of 00 and 01 for drives 0 and 1 respectively. The drive selection qualification is only completed when either bit 4 (for drive 0) or bit 5 (for drive 1) is set. In addition setting bits 4 or 5 will have no effect until the value of DS1, DS0 is correspondingly set.

Bit 2 when cleared (0) holds the 765A reset until bit 2 is again set (1). Note that a reset must last for at least 3.5 uS.

On power-up or following a system reset, all bits in this register are cleared to zero.

1.12.1 FDC Hardware Conditions

The hardware imposes the following conditions on the use of the 765A controller and disk drives:

  1. The clock frequency of the 765A FDC is fixed at 4.0 MHz.
  2. Disk data transfers are done by DMA using the on-board DMA controller. The 765A DRQ output may connected to or disconnected from the DMA controller DRQ2 input by software using Drive Selection Register bit 3.
  3. An interrupt level is available for use by the 765A to signal command completion and attention status to the CPU. The 765A INT output may be connected to or disconnected from the interrupt controller IRQ6 input by software using Drive Selection Register bit 3.
  4. Drive 0 is always present. Drive 1 is optional. Drives 2 and 3 are not implemented and can never be accessed. Drive Ready output signal from the currently selected drive is connected to the 765A RDY input. For drives which do not a drive ready output the 765A RDY input may be optionally fixed to the true condition.
  5. The 765A Drive Select outputs US1 and US0 are not used to select the drives. This function together with motor control is done via the Drive Selection Register which is external to the FDC 765A.
  6. The FLT (Fault) input 765A is forced permanently false.
  7. A Two-Sided status signal from the drive(s) is not provided but interface to the drives allows the use of double sided drives.
  8. Write precompensation of 250 nS is provided.
  9. The 765A may be individually reset by software using Drive Selection Register bit 2.

1.13 RS232C Asynchronous Serial Port

The asynchronous serial port is based on the National INS8250 ACE (or UART), single channel device.

The clock frequency input of the 8250 is 1.8432 MHz (± 0.1%).

The 8250 BAUD OUT output is connected to the RCLK input.

An interrupt level is available for use by the 8250. When the 8250 OUT2 output is driven low (i.e. a 1 is written to bit 2 of the 8250 MODEM Control Register) then the INTRPT signal is connected to the interrupt control IRQ4 input.

1.13.1 Serial Channel Interface

The serial interface uses a 25-way subminiature D type plug (male) connector emulating a DTE (Data Terminal Equipment).

The electrical levels of signal lines on this interface conform with EIA (Electronics Industry Association) standard RS-232C (and the equivalent V.24 interface standard).

The RS232C drivers and receivers between the 8250 and the serial channel connector are all inverting.

1.13.2 Serial Channel Pin Arrangement

1AA101Frame Ground
2BA103TxD - Serial Data Output
3BB104RxD - Serial Data Input
*4CA105RTS - Request to Send Output
5CB106CTS - Clear to Send Output
6CC107DSR - Data Set Ready Input
7AB102Signal Ground (Common Return)
8CF109DCD - Data Carrier Detect Input
*20CD108.2DTR - Data Terminal Ready Output
22DE125RI - Ring Indicator Input

* These interchange circuits, where implemented, shall be used to detect either a power off condition in the equipment across the interface, or the disconnection of the interconnecting cable. The terminator for these circuits shall interpret the power off condition or the disconnection of the interconnecting cable as an OFF condition.

[RS232 pinout]
Viewed from rear of machine

See Appendix 3 for additional details of serial signals and cable connections.

1.14 Parallel Printer Interface

The parallel printer port is described in Section 1.10 and is a general purpose 'centronics' style 8-bit interface. The printer interface uses a 25-way subminiature 'D' socket (female) connector located at the back of the PC1512.

The Pin assignments for the printer connector is as follows:

1Data Strobe [Parallel pinout]
Viewed from rear of machine
2Data Bit 0
3Data Bit 1
4Data Bit 2
5Data Bit 3
6Data Bit 4
7Data Bit 5
8Data Bit 6
9Data Bit 7
10Printer Acknowledge
11Printer Busy
12Paper Out
13Select Printer
14Select Auto Feed
15Printer Error
16Reset Printer
17Printer Selected

Appendix 4 contains the Amstrad PL-2 printer lead specification for the DMP3000 printer.

1.15 Keyboard Interface

Keyboard data input to the CPU is via the 8255 PPI Port A, and the keyboard interrupt (level 1) of the 8259A PIC. Both of these have been previously described in sections 1.6 and 1.8.

1.15.1 Serial Clock and Serial Data

The Serial Clock and Serial Data signals are used for keyboard interface. These two bidirectional signals are used by the keyboard microcontroller to send keycodes to the main electronics board. The main electronics board also uses the same two signals to indicate readiness to receive another keycode back to the microcontroller. In addition these two signals are used to reset the microcontroller under hardware or software control.

1.15.2 Keyboard to Main Board Interface

The quiescent state for both Serial Clock and Serial Data is high. A minimum of 5 uS must separate a transition of one signal from another transition of the same signal, or any transition of the other signal.

Keycodes are sent from the keyboard microcontroller to the main board in 8-bit serial form MS bit first. Keycode data received by the main board is clocked into a shift register as either a "1" bit sequence or as a "0" bit sequence. To be interpreted as a "1" bit, the Serial Data signal must remain high during the time period when Serial Clock goes low and returns to the high state. To be interpreted as a "0" bit, Serial Data must be low prior to the Serial Clock transition from high to low, Serial Data will then go high followed by Serial Clock. The "1" bit or the "0" bit is clocked into the shift register on the falling edge of Serial Clock.

1.15.3 Main Board to Keyboard Interface

Upon receiving a keystroke from the microcontroller, within 5 uS of the last clock falling edge, the main board electronics drives the Serial Data line low and maintains it low until it is ready to receive a new keystroke. When the main board returns the Serial Data signal to the high state the microcontroller is free to send another keystroke. This response to the reception of a keycode is termed the ACKNOWLEDGE sequence.

The mainboard electronics causes a RESET to the keyboard microcontroller by driving the Serial Clock line low for 10 milliseconds or more. The state of the Serial Data signal does not affect the reset sequence.

1.15.4 Keycodes

The 8-bit keyboard data is capable of 128 make codes correspondingly 128 break codes. For any key which is pressed, the ( make ) keycode produced is in the range of 0 - 127 decimal. When a key is released, the ( break ) keycode produced is the same as the make keycode except that the top bit is set so that the value is in the range of 128 - 511 (decimal). The keycodes and their corresponding token values are covered in the ROS firmware (Section 2.3.5).

After a key is pressed and the keycode has been sent to the main board electronics, if no new keys are pressed and the key has remained pressed for more than one second, then the keyboard microcontroller re-sends the keycode every 83 milliseconds provided that the main board indicates by an Acknowledge sequence that is ready to accept a new keycode.

The keycode AA hexadecimal is sent after a reset to indicate successful completion of power-up tests.

1.15.5 Keyboard Connector

The Keyboard connector is a 6-way Din socket. The pin assignment is as follows:

1KBCLK Viewed from left hand side of machine
[Keyboard pinout]
5+5 Volts DC

The M1 and M2 signals are connected directly to the keyboard controller in order to produce keycodes.

1.16 Mouse Interface

The mouse interface consists of two switch inputs from push buttons and two 8-bit X & Y coordinate counters. The two mouse switches (M1 & M2) are arranged to form part of the keyboard matrix and are handled as keyboard data (producing low level keycodes 7E and 7D respectively).

The Mouse X-Coordinate at I/O Address 078 is an 8-bit counter which can be read by the CPU. Any write access regardless of the value written to the X-Coordinate location clears the counter. Similarly the Mouse Y-Coordinate at I/O Address 07A can be read by the CPU or cleared by any write access to its I/O address.

The counters are incremented or decremented according to the direction of movement of the mouse, and their values indicate the mouse movement since last read or cleared. The X-Coordinate counter increments for "Right" motion and decrements for "Left" motion. The Y-Coordinate counter increments for "UP" motion and decrements for "Down" motion. In order to properly track mouse motion, software should read and clear the coordinate counters at a rate high enough to prevent overflow from positive values to negative values or negfative values to positive values for a fairly high rate of mouse movement. The scaling of mouse movement is such that one increment of the counter represents 1/8 mm of physical mouse motion.

The delivered operating systems have AMSTRAD specific mouse drivers which actively perform the Read-and-Clear operation (every 18 ms) using the ticker interrupt. This can cause the appearance of no mouse motion to the casual observer sampling the mouse coordinate counters. See Appendix 1 for additional details concerning Mouse Software Interfaces.

1.16.1 Mouse Connector

The mouse connector is a 9 way D type (female) connector located on the left hand side of the case and it has an AMSTRAD specific pinout. Attaching any other manufacturer's hardware (even though the connector may be similar) to the PC1512 mouse connector may cause serious damage to either the main board electronics or to the alternative (mouse) hardware.

The mouse connector pin assignments are as follows:

7+5 Volts DC

The first four pins contain optically encoded phase XA, XB, YA and YB square waves. For positive motion the square wave on the A phase leads the B phase by 90 degrees with the reverse being true for negative motion.

The remaining pins carry Mouse Button 1 (M1), 5V power, Ground and Mouse Button 2 (M2) signals.

[Mouse pinout]
Viewed from left hand side of machine

1.17 Joystick Interface

The AMSTRAD PC supports an industry standard joystick interface. The joystick inputs are handled as keycodes from the keyboard interface. The low level keycodes are in the range of 7C down to 77 (hexadecimal) corresponding to Up, Down, Left, Right, Fire1 and Fire2 respectively. The ROS firmware (See section 2) translates the directional codes to cursor key tokens and the Fire buttons can be assigned variable tokens depending on the NVR settings. Please note that this is not an analog interface. In order to use an analog joystick an analog card for the expansion slots is required.

1.17.1 Joystick Connector

The joystick connector is a 9 way D type (male) connector with an industry standard pinout. Attaching an incorrect device (even though the connector may be similar) to the PC1512 joystick connector may cause serious damage to either the main board electronics or to the incorrect (joystick) hardware.

The Joystick Socket is located on the rear left corner of the keyboard. Its pinout is as follows:

6Fire 2
7Fire 1
9Not Connected

[Joystick pinout]
Viewed from rear of keyboard

1.18 Light Pen Connector

The AMSTRAD PC1512 Supports a standard light pen interface via the emulated MC6845. The Light Pen connector is located by removing the expansion slot cover at the rear of the machine. The connector is located inside the PC case on the right hand edge of the main board just forward of the expansion card connectors. It consists of a 6-way berg strip and is labeled PL8 (LIGHT PEN) in large letters. Pin 1 is the forward most pin viewed from in front of the machine (the disk drive end).

The pin assignment is as follows:

1Light Pen Input.
3Light Pen Switch.
5+5 Volts DC.
6+12 Volts DC.

[Lightpen pinout]

1.19 Expansion Card Interface

The AMSTRAD PC1512 has three slots for additional peripheral cards. These consist to a set of connectors in the right rear of the main board. The Pin numbering of the each connector is the same and is such that the left (ground plane) side is numbered B1 - B31 top to bottom and the right (component) side is numbered A1 - A31 top to bottom. The following table defines the pin assignments of the expansion interface:

A02I/O Data Bit D7In/Out
A03I/O Data Bit D6In/Out
A04I/O Data Bit D5In/Out
A05I/O Data Bit D4In/Out
A06I/O Data Bit D3In/Out
A07I/O Data Bit D2In/Out
A08I/O Data Bit D1In/Out
A09I/O Data Bit D0In/Out
A11AEN - Address EnableOut
A12I/O + Mem/Address Bit A19Out
A13I/O + Mem/Address Bit A18Out
A14I/O + Mem/Address Bit A17Out
A15I/O + Mem/Address Bit A16Out
A16I/O + Mem/Address Bit A15Out
A17I/O + Mem/Address Bit A14Out
A18I/O + Mem/Address Bit A13Out
A19I/O + Mem/Address Bit A12Out
A20I/O + Mem/Address Bit A11Out
A21I/O + Mem/Address Bit A10Out
A22I/O + Mem/Address Bit A09Out
A23I/O + Mem/Address Bit A08Out
A24I/O + Mem/Address Bit A07Out
A25I/O + Mem/Address Bit A06Out
A26I/O + Mem/Address Bit A05Out
A27I/O + Mem/Address Bit A04Out
A28I/O + Mem/Address Bit A03Out
A29I/O + Mem/Address Bit A02Out
A30I/O + Mem/Address Bit A01Out
A31I/O + Mem/Address Bit A00Out
B03+ 5 Volts DC--
B05- 5 Volts DC--
B07- 12 Volts DC--
B08Not Connected (Reserved)In
B09+ 12 Volts DC--
B11MEW (Memory Write)Out
B12MRD (Memory Read)Out
B13IOW (I/O Write)Out
B14IOR (I/O Read)Out
B29+ 5 Volts DC--

[Expansion bus pinout]
Expansion Bus Connector
Viewed from above while standing in front of machine

The I/O expansion slots are laid out the same as the industry standard 16-bit Personal Computer bus. The translation from the internal 16-bit 8086 bus to the 8-bit I/O bus layout is done by main board circuitry. Any 16-bit CPU I/O transfers will be broken down into two 8-bit cycles (with wait states) by this circuitry.

All signals are TTL compatible and can support a maximum of two low-power schottky (LSTTL) loads per slot. Power supply loading per slot should be limited to a maximum of 900 milliamperes on the + 5 Volt supply, to 33 milliamperes on the - 5 Volt supply, to 50 milliamperes on the + 12 Volt supply and to 50 milliamperes on the - 12 Volt supply. See Appendix 6.

Note that direct access to the on-board 16-bit fast memory bus is not available via the I/O expansion slots.

Additional engineering details for prototyping adapter boards should be supplied as part of the documentation for that particular hardware.

1.20 Video Connector

The video connector is a 8-way Din socket located in the rear of the computer. Its pinout is as follows:

1Composite H & V sync [Monitor pinout]
Video Plug (from monitor)

1.21 Power Connector

The power connector is a 14-way Din socket located in the rear of the computer. Power is routed from the power supply located in the monitor to the main board electronics through the power connector. Its pinout is as follows:

PinAssignmentMAX CURRENT
1Not Connected Power Plug (from monitor)
[Power pinout]
20 Volts DC
3+ 5 Volts DC- (SEE NOTE 1)
40 Volts DC
5+ 5 Volts DC- (SEE NOTE 1)
6Not Connected
7Not Connected
80 Volts DC
9- 12 Volts DC0.24 AMP
100 Volts DC
11+ 12 Volts DC4.9 AMP
120 Volts DC
13- 5 Volts DC1 AMP
14Not Connected

Note 1: Pins 3 & 5 are connected together to the +5 V bus for a total of 7.00 Amp maximum rating.

Note 2: See Appendix 6 for Power consumption data.

Contents Index Section 2