Section 2 Index Appendices

SECTION 3 - TABLES

3 Reference Information

The following tables document a number of the hardware and software features of the AMSTRAD PC1512 some of which may have been already mentioned in earlier sections but are repeated here for easy reference.

3.1 Language Links.

The lower three bits of the Printer Status Channel (I/O address 379) are wired to reflect the (one's complement) state of a set of option links (LK1 - LK3) located on the left side of the main board about 2 inches below the printer connector. They are used by the ROS firmware to define the language option or diagnostic mode option as detailed below.

Link ValueROS Usage
0English Language.
1German Language.
2French Language.
3Spanish Language.
4Danish Language.
5Swedish Language.
6Italian Language.
7Diagnostic Mode.

The ROS messages are displayed in the selected languge. In diagnostic mode, the messages revert to English, and the normal testing is skipped. Any self test failures are reported but are ignored and upon completion a disk bootstrap is attempted. This enables loading of an extended set of diagnostic software.

3.2 Processor Memory Usage.

The following is a repeat of the processor's physical memory layout in tabular form with interrupts and ROS areas included.

Location(s) Usage
00000 - 003FF Processor interrupt vectors 0 to 255. To derive an individual interrupt vector's starting address multiply the vector number by four.
00400 - 00500 ROS Variables. (See section 2.4)
00501 - 7FFFF System (or User) RAM artea. The 512K byte area (inclusive of the previous entries) is the normal complement of system memory installed.
80000 - BFFFF 128K Byte area where additional memory may be installed in external 32K byte increments.
A0000 - BFFFF 128K byte area reserved for 8-bit controller memory. The standard VDU screen memory resides in the address range from B8000 to BBFFF. Individual peripheral cards may make use of the other addresses as they see fit. For additional details, consult the manual supplied the card or its manufacturer's agent.
C0000 - EFFFF 192K byte area reserved for the expansion ROMs of the various peripheral cards. The optional Hard Disk controller uses the address range from C8000 to CBFFF.
E0000 - FFFFF 64K byte area reserved for System ROM. The ROS resides in the 16K byte area from FC000 to FFFFF. The remaining 48K bytes is reserved for future expansion. Address block occurs repeat from 16K byte ROS area occurs in this range.

3.3 Keyboard and Key Codes.

Key CodeHex(UK) Key Cap
101ESC
2021 and !
3032 and "
4043 and £
5054 and $
6065 and %
7076 and ^
8087 and &
9098 and *
100A9 and (
110B0 and )
120C- and _
130D= and +
140E<-DEL
150FTAB
1610Q
1711W
1812E
1913R
2014T
2115Y
2216U
2317I
2418O
2519P
261A[ and {
271B] and }
281CCR (↵)
291DCTRL
301EA
311FS
3220D
3321F
3422G
3523H
3624J
3725K
3826L
3927; and :
4028' and @
4129# and ~
422ALEFT SHIFT
432B\ and |
442CZ
452DX
462EC
472FV
4830B
4931N
5032M
5133, and <
5234. and >
5335/ and ?
5436RIGHT SHIFT
5537* and PRTSC
5638ALT
5739SPACE
583ACAPS LOCK
593BF1
603CF2
613DF3
623EF4
633FF5
6440F6
6541F7
6642F8
6743F9
6844F10
6945NUM LOCK
7046SCROLL LOCK
7147KEY PAD 7
7248KEY PAD 8
7349KEY PAD 9
744AKEY PAD -
754BKEY PAD 4
764CKEY PAD 5
774DKEY PAD 6
784EKEY PAD +
794FKEY PAD 1
8050KEY PAD 2
8151KEY PAD 3
8252KEY PAD 0
8353KEY PAD .
84 - 11154 - 6FUNDEFINED
11270DEL ->
113 - 11571 - 73UNDEFINED
11674ENTER
117 - 11875 - 76UNDEFINED
11977JOY FIRE2
12078JOY FIRE1
12179JOY RIGHT
1227AJOY LEFT
1237BJOY DOWN
1247CJOY UP
1257DMOUSE M2
1267EMOUSE M1
1277FUNDEFINED

3.4 Asynchronous Communications Element (8250) Registers.

For serious design purposes, it is recommended that the designer obtain the standard INS8250 data sheets. The following excerpt are the major software accessible registers.

Modem Status Register (MSR) [R6] - I/O Address 3FEh.

Bit(s)Function
7Data Carrier Detect (DCD).
6Ring Indicator (RI).
5Data Set Ready (DSR).
4Clear To Send (CTS).
3Delta Data Carrier Detect (DDCD).
2Trailing Edge Ring Indicator (TREI).
1Delta Data Set Ready (DDSR).
0Delta Clear To Send (DCTS).

Line Status Register (LSR) [R5] - I/O Address 3FDh.

Bit(s)Function
7Always Clear (0).
6Transmitter Shift Register Empty (TSRE).
5Transmitter Holding Register Empty (THRE).
4Break Interrupt (BI).
3Framing Error (FE).
2Parity Error (PE).
1Overrun Error (OE).
0Data Ready (DR).

Modem Control Register (MCR) [R4] - I/O Address 3FCh.

Bit(s)Function
7Always Clear (0).
6Always Clear (0).
5Always Clear (0).
4Loop (Diagnostic Mode).
3Out2 (Looped to RI).
2Out1 (Looped to DCD).
1Request to Send (RTS) (Looped to DSR).
0Data Terminal Ready (DTR) (Looped to CTS).

Line Control Register (MCR) [R3] - I/O Address 3FBh.

Bit(s)Function
7Divisor Latch Access (DLAB) (Selects Regs 0 & 1).
6Set Break.
5Stick Parity (Holds parity as EPS not if PEN set).
4Even parity Select (EPS).
3Parity Enable (PEN).
2Number of Stop Bits (STB) (0=1 Stop Bit, 1= >1).
1Word Length Select Bit 1 (WLS1). (0-3 = 5-8 Bits)
0Word Length Select Bit 0 (WLS0).

Interrupt Identification Register (IIR) [R2] - I/O Address 3FAh.

Bit(s)Function
7Always Clear (0).
IID Int Type
3 Rx Line Status
2 Rx Data Avail.
1 Tx H.Reg Empty
0 MODEM Status
6Always Clear (0).
5Always Clear (0).
4Always Clear (0).
3Always Clear (0).
2Interrupt ID Bit 1 (IID1).
1Interrupt ID Bit 0 (IID0).
0Not Interrupt Pending.

Interrupt Enable Register (IER) [DLAB = 0:R1] - I/O Address 3F9h.

When the Divisor Access Latch Bit (Line Control Register bit 7: DLAB) is clear, inputting I/O address 3F9 reads the IER.

Bit(s)Function
7Always Clear (0).
6Always Clear (0).
5Always Clear (0).
4Always Clear (0).
3Modem Status (EDSSI).
2Receiver Line Status (ELSI).
1Transmitter Holding Register Empty (ETBEI).
0Received Data Available (ERBAI).

Receive Buffer Register (RBR)
Transmit Holding Register (THR) [DLAB = 0:R0] - I/O Address 3F8h.

When the Divisor Access Latch Bit (Line Control Register bit 7: DLAB) is clear, reading and writing I/O location 3F8 accesses the RBR/THR registers. An input from I/O address 3F8 reads the Receiver buffer Register (bits 0 to 7). Outputting to I/O address 3F8 writes the Transmitter holding Register.

Divisor Latches MS & LS (DLL & DLM) [R0 & R1 when DLAB Set].

When the Divisor Access Latch Bit (Line Control Register bit 7: DLAB) is set, then registers 0 & 1 are the (16-bit) Divisor Register. The least significant bits are written to by outputting to address 3F8 and the most significant bits are written to by an output to location 3F9. The divisors and their respective baud rates are as follows.

Baud RateDivisorR1 & R0 (hex)
75153606 - 00
30038401 - 80
60019200 - C0
12009600 - 60
24004800 - 30
48002400 - 18
96001200 - 0C

3.5 High Performance Programmable DMA Controller (8237A-4) Registers.

The following are the major software accessible 8237A registers.

Command Register - Write I/O Address 008.

Bit(s)Function (Action ... { 1 / 0 })
7DACK sense active { hi / lo }.
6DREQ sense active { hi / lo }.
5{Extended/Late} write selection.
4{Rotating/Fixed} priority.
3{Compressed/Normal} timing.
2{Disable/Enable} Controller.
1{Enable/Disable} Channel 0 address hold.
0{Enable/Disable} Memory-to-memory (not supported).

Status Register - Read I/O Address 008.

Bit(s)Function
7Channel 3 Request.
6Channel 2 Request.
5Channel 1 Request.
4Channel 0 Request.
3Channel 3 has reached TC.
2Channel 2 has reached TC.
1Channel 1 has reached TC.
0Channel 0 has reached TC.

Mode Register - I/O Address 00B [WO].

Bit(s)Function
7Mode Select Bit 1. (Modes: 0 = Demand, 1 = Single,
6Mode Select Bit 0. 2 = Block, 3 = Cascade)
5Address {decrement/increment} select.
4Autoinitialisation {enable/disable}.
3Transfer Type Bit 1. (Modes: 0 = Verify, 1 = Write,
2Transfer Type Bit 0. 2 = Read, 3 = Illegal)
1Channel Select Bit 1. (Channels: 0-3 respectively)
0Channel Select Bit 0.

Request Register - I/O Address 009h [WO].

Bit(s)Function
7Don't Care.
6Don't Care.
5Don't Care.
4Don't Care.
3Don't Care.
2Request Bit {Set/Reset}.
1Channel Select Bit 1. (Channels: 0-3 respectively)
0Channel Select Bit 0.

Mask Set/Reset Register - I/O Address 00Ah [WO].

Bit(s)Function
7Don't Care.
6Don't Care.
5Don't Care.
4Don't Care.
3Don't Care.
2{Set/Reset} Mask Bit.
1Channel Select Bit 1. (Channels: 0-3 respectively)
0Channel Select Bit 0.

Mask Write Register - I/O Address 00F [WO].

Bit(s)Function
7Don't Care.
6Don't Care.
5Don't Care.
4Don't Care.
3{Set/Clear} Channel 3 Mask Bit.
2{Set/Clear} Channel 2 Mask Bit.
1{Set/Clear} Channel 1 Mask Bit.
0{Set/Clear} Channel 0 Mask Bit.

3.6 Programmable Interrupt Controller (8259A-2) Command Words.

The Initialisation Command Word (ICW) sequence is as follows:

Initialisation Command Word 1 (ICW1) - Write I/O Address 020.

Bit(s)Function (Action ... { 1/0 })
7N/A.
6N/A.
5N/A.
4Always Set (1)
3{Level/Edge} Trigger Mode.
2Call Address Interval of {4/8}.
1{Single/Cascade} Mode (Need ICW3 if Single Mode).
0ICW4 {Needed/Not Needed}.

Initialisation Command Word 2 (ICW2) - Write I/O Address 021h.

Bit(s)Function (Action ... { 1/0 })
7Interrupt Type Bit 7 (T7).
6Interrupt Type Bit 6 (T6).
5Interrupt Type Bit 5 (T5).
4Interrupt Type Bit 4 (T4).
3Interrupt Type Bit 3 (T3).
2Not used.
1Not used.
0Not used.

This byte selects one of the interrupt service vector locations (in absolute locations 0 through 3FF) to be used when interrupting. Type bits 3 - 7 (asserted on the data bus during the INTA cycle) map to address bits 5 - 9 for interrupt vector selection. The lower three type bits are derived from the interrupt level.

Initialisation Command Word 3 (ICW3) - Write I/O Address 021.

This command word is not used since Single (ICW1 bit 1) is always true in the PC1512. When used, this command word specifies which IR has a slave in Master mode, or it a slave then bits 0 through 3 specify the slave ID number (0 to 7).

Bit(s)Function (Action ... { 1/0 })
7Always clear (0).
6Always clear (0).
5Always clear (0).
4{Enable/Disable} Special Fully Nested Mode.
3Buffered Mode {On/Off}.
2{Master/Slave} Mode (Only valid in Buffered Mode).
1{Auto/Normal} EOI.
0Always set (1) - (8086/8088 Mode).

Operation Control Words

The operation control words select various 8259A modes of operation.

Operation Control Word 1 (OCW1) - Write I/O Address 021.

Bit(s)Function (Action ... { 1/0 })
7Interrupt Mask 7 {Set/Reset}.
6Interrupt Mask 6 {Set/Reset}.
5Interrupt Mask 5 {Set/Reset}.
4Interrupt Mask 4 {Set/Reset}.
3Interrupt Mask 3 {Set/Reset}.
2Interrupt Mask 2 {Set/Reset}.
1Interrupt Mask 1 {Set/Reset}.
0Interrupt Mask 0 {Set/Reset}.

The eight mask bits either mask (i.e. inhibit when M=1) or enable their respective channels.

Operation Control Word 2 (OCW2) - Write I/O Address 020.

Bit(s)Function
7Rotate (R) Bit.
6Specific (SL) Bit.
5End of Interrupt (EOI) bit.
4Always zero.
3Always zero.
2Level bit 2 (L2).
1Level bit 1 (L1).
0Level bit 0 (L0).

The level bits are required when specific (SL) is set.

Operation Control Word 2 (OCW2) - Write I/O Address 020.

Bit(s)Function (Action ... { 1/0 })
7Always zero.
6Enable Special Mask Mode (ESMM) bit.
5Special Mask Mode (SMM) {Set/Reset}.
4Always zero.
3Always set.
2{Enable/Disable} Poll Command.
1Read Register (RR) enable bit.
0Read {IS/IR} register on next -RD pulse (RIS).

The ESMM bit must be set for the SMM bit to have any effect. Similarly the RR bit must be set for the RIS bit to have an effect.

3.7 Programmable Interval Timer (8253) Registers.

The 8253 PIT has four addressable elements, the three counters (0 - 2) which are read or written 8 bits at a time (on I/O addresses 40 - 42) and the Control Word register (write I/O address 043).

Bit(s)Function (Action ... { 1/0 })
7Select Counter bit 1 (SC1).
6Select Counter bit 0 (SC0).
5Read/Load bit 1 (RL1).
4Read/Load bit 0 (RL0).
3Mode bit 2 (M2).
2Mode bit 1 (M1).
1Mode bit 0 (M0).
0{Enable/Disable} Binary Coded Decimal (BCD) counter.

The SC bits select counters 0-2 and the 3 (both bits set) state is illegal.

The RL bits enable the counter's Read/Load operation as follows:

0:
Counter Latching - Snapshot current counter (to a holding register) for next read operation.
1:
Read/Load MS byte only.
2:
Read/Load LS byte only.
3:
Read/Load LS byte first then the MS byte.

The Mode bits select one of five valid modes (six & seven wrap around to modes two and three). The modes are as follows:

0:
Interrupt on Terminal count.
1:
Programmable One-Shot.
2:
Rate Generator.
3:
Square Wave generator..
4:
Software Triggered Strobe.
5:
Hardware triggered Strobe.

3.8 Real Time Clock (HD146818) Registers.

The HD146818 is a CMOS peripheral device which combines three unique features: a complete time-of-day clock with an alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static RAM.

The figure below shows the address map of the HD146818. The memory consists of 50 bytes of general purpose RAM, 10 RAM bytes which normally contain the time, calendar, and alarm data, and four control and status bytes. All bytes are directly readable readable and writable by the processor except Registers C and D which are read only. Bit 7 of Register A and the seconds byte are also read only.

0Seconds00
1Sec Alarm01
2Minutes02
3Min Alarm03
4Hours04
5Hr Alarm05
6Day of Wk06
7Day of Mo07
8Month 08
9Year 09
10Register A0A
11Register B0B
12Register C0C
13Register D0D

140E
50
Bytes
User
RAM
633F

Time, Calendar and Alarm Locations

The processor obtains time and calendar information by reading the appropriate locations. The program may initialise the time, calendar and alarm by writing these locations. The contents of the 10 time, calendar and alarm bytes may either be binary or binary-coded decimal (BCD).

Before initialising the internal registers the SET bit in register B should be set to a "1" to prevent time/calendar updates from occurring. The program initialises the 10 locations in the selected format (binary or BCD), then indicates the format in the data mode (DM) bit of register B. All 10 locations must use the fame data mode, either binary or BCD. The SET bit may now be cleared to allow updates. Once initialised the real-time clock makes all updates in the selected data mode. The data mode cannot be changed without reinitialising the 10 data bytes.

The table below shows the binary and BCD formats of the time, calendar and alarm locations.

Address Function Range Binary Data Mode BCD Data Mode
0Seconds 0-59 00h-3Bh00h-59h
1Sec Alarm 0-5900h-3Bh 00h-59h
2Minutes 0-5900h-3Bh 00h-59h
3Min Alarm 0-5900h-3Bh 00h-59h
4 Hours 01h-0Ch (AM) 01h-12h (AM)
12-Hr Mode1-12 81h-8Ch (PM) 81h-92h (PM)
24-Hr Mode 0-23 00h-17h00h-23h
5 Hrs Alarm 01h-0Ch (AM) 01h-12h (AM)
12-Hr Mode1-12 81h-8Ch (PM) 81h-92h (PM)
24-Hr Mode 0-23 00h-17h00h-23h
6Day of Wk 1-7 01h-07h01h-07h
7Day of Mon 1-31 01h-1Fh01h-31h
8Month 1-12 01h-0Ch01h-12h
9Year 0-99 00h-63h00h-99h

For the Day of the Week, Sunday = 1.

The 24/12 bit in register B establishes whether the hour locations represent 1-to-12 or 0-to-23. The 24/12 bit cannot be changed without reinitialising the hour locations. When the 12-hour format is selected the high-order bit of the hours represents PM when it is a "1". The time, calendar and alarm bytes are not always accessible by the processor. Once per second the 10 bytes are switched to the update logic to be advanced by one second and to check for an alarm condition. If any of the 10 locations are read at this time, the data outputs are undefined. The update-in-progress (UIP) bit in Register A may be used to determine if the update cycle is in progress or not. The UIP bit goes high once a second and the update cycle begins 244 uS later. Therefore, if a "0" is read on the UIP bit, the user has at least 244 uS before the time/calendar data will be changed.

RTC Register Locations

The HD 146818 has four registers which are accessible to the processor. The four registers are fully accessible during the update cycle.

The bit assignments for Register A (address 0Ah) are as follows:

BitAssignment
7Update In Progress (UIP)
6Divider Bit 2 (DV2)
5Divider Bit 1 (DV1)
4Divider Bit 0 (DV0)
3Rate Selection Bit 3 (RS3)
2Rate Selection Bit 2 (RS2)
1Rate Selection Bit 1 (RS1)
0Rate Selection Bit 0 (RS0)

The UIP bit indicates whether the 10 time, calendar and alarm bytes are being updated or not as explained above.

The three Divider bits (DV2-DV0) are used to identify which of the three time base frequencies is in use or to reset the divider chain.

The four rate selection bits (RS3-RS0) select one of 15 taps on the 22-stage divider chain, or disable the divider output. The tap selected may be used to generate an output on the square (SQW) pin and/or a periodic interrupt.

The bit assignments for Register B (address 0Bh) are as follows:

BitAssignment
7SET Bit
6Periodic Interrupt Enable (PIE) Bit
5Alarm Interrupt Enable (AIE) Bit
4Update-ended Interrupt Enable (UIE) Bit
3Square-Wave Enable (SQWE) Bit
2Data Mode (DM) Bit
112/12 hour format Bit
0Daylight Savings Enable (DSE) Bit

When the SET bit is a "0" the update cycle functions normally by advancing the counts once per second. When the SET bit is written to a "1", any update cycle in progress is aborted and the processor may initialise the time and calendar locations without updates occurring. SET is a read/write bit which is not modified by RES or internal functions of the HD146818.

The PIE bit is a read/write bit which allows the periodic-interrupt (PF) bit to cause the IRQ pin to be driven low. The program writes a "1" to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3 RS0 bits in Register A. A "0" in PIE blocks 'IRQ from being generated, bu the periodic flag (PF) bit still goes high at the periodic rate.

The AIE bit is a read/write bit which when set to "1" permits the alarm flag (AF) to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes. When AIE is a "0" the AF bit does not initiate an IRQ. The RES pin clears AIE to "0". The internal functions do not affect the AIE bit.

The UIE bit is a read/write bit which enables the update-end flag (UF) bit to assert IRQ. The RES pin going low or the SET bit going high clears the UIE bit.

When the SQWE bit is set to a "1" by the processor, a square-wave signal at the frequency specified by the rate selection bits (RS3 to RS0) appears on the SQW pin. When the SQWE bit is set to "0" the SQW pin is held low. The SQWE bit is cleared by the RES pin. SQWE is a read/write bit.

The DM bit indicates whether time and calendar updates are to use binary or BCD format. DM is a read/write bit and is not modified by RES or internal functions of the HD146818. A "1" in DM signifies binary data and a "0" specifies BCD data mode.

The 24/12 control bit specifies the format of the hour bytes. A "1" specifies 24-hour mode and a "0" specifies 12-hour mode. It is a read/write bit and is not affected by RES or any HD146818 internal functions.

The DSE bit is a read/write bit which when set to "1" enables daylight savings mode. When enabled, two special updates take place. On the last sunday in April the time increments from 1:59:59 to 3:00:00 AM. On the last sunday in October when the time first reaches 1:59:59 AM is decremented to 1:00:00 AM. DSE is not changed by RES or any internal operations.

The bit assignments for Register C (address 0Ch) are as follows:

BitAssignment
7Interrupt Request Flag (IRQF) Bit
6Periodic Interrupt Flag (PF) Bit
5Alarm Interrupt Flag (AF) Bit
4Update-Ended Interrupt Flag (UF) Bit
30
20
10
00

The C register is a read-only register and a program write has no effect any of the bits.

The IRQF bit is set by the logical equation: IRQF = PF⋅PIE + AF⋅AIE + UF⋅UIE. Any time the IRQF bit is a "1", the IRQ pin is driven low. All flag bits in the C register are cleared after a program read or when the RES pin is low.

The PF bit is set to "1" when a particular edge is detected in the selected tap of the divider chain as selected by the RS3 to RS0 bits. The PF bit is set to a "1" independent of the state the PIE bit.

The AF bit is set to a "1" when the current time matches the alarm time.

The UF bit is set after each update cycle.

The remaining bits (3 to 0) are always low.

The bit assignments for Register D (address 0Dh) are as follows:

BitAssignment
7Valid RAM Time (VRT) Bit
60
50
40
30
20
10
00

The VRT bit indicates that the contents of the RAM and time are valid. A "0" appears in the VRT bit when the power sense (PS) pin is low. The processor can set the VRT bit when the time and calendar are initialised to indicate that they are valid. The VRT bit is a read-only bit and is not modified by the RES pin. The VRT bit can only be set by reading the D register.

Bits 6 to 0 are unused and are always read as zeroes.

3.9 Floppy Disk Controller (uPD765A).

The uPD765A Floppy Disk Controller (FDC) contains two registers which are accessible to the CPU; the Main Status Register (at I/O address 03F4) and the Data Register (at I/O address 03F5) both of which are 8 bits wide. The Status register contains the status of the FDC and may be accessed at any time. The Data Register is actually made up of several registers in a stack and stores data, commands and Floppy Disk Drive (FDD) status information. Data is written into the data register in order to program a particular command. The data address is read in order to obtain the result after an operation. The Main Status register (I/O address 3F4h) may only be read and is used to facilitate the transfer of data between the CPU and the uPD765A FDC.

There are 15 separate commands which the uPD765A FDC can execute. Each of these commands require multiple bytes to fully specify the operation. The result after execution of the command may also be a multi-byte transfer back to the processor. Because of this multi-byte interchange of information between the processor and the FDC, it is convenient to consider each command as consisting of three phases:

Command Phase:
The FDC accepts all information to perform a particular operation from the CPU.
Execution Phase:
The FDC performs the operation.
Result Phase:
After completion of the operation, status and housekeeping information are made available to the CPU.

The uPD765A contains five status registers. The main status register mentioned earlier which may be read at any time and four result phase status registers (ST0, ST1, ST2 and ST3) which are only made available during the Result Phase after completion of a command. The particular command which has been executed determines which status registers will be returned.

The Command bytes which are sent to the uPD765A during the Command Phase must occur in the order shown in the command table. That is, the command code must be sent first followed by the other bytes in the prescribed sequence. No foreshortening of the Command Phase or the Result Phase is allowed. After the last byte of data in the Command Phase is sent the Execution Phase automatically starts. In a similar fashion, when the last byte of data is read out in the Result Phase, the command is automatically ended and the uPD765A is ready for a new command.

It is important to note that during the Result phase all bytes shown in the Command table msut be read. The Read Data command, for example has seven bytes listed in the result phase. All seven bytes must be read out else a new command will not be accepted.

The status registers as follows:

Main Status Register

Bit(s)Function
7Request for Master (RQM).
6Data Input/Output (DIO).
5Execution Mode (EXM).
4FDC Busy (CB).
3FDD 3 Busy (D3B).
2FDD 2 Busy (D2B).
1FDD 1 Busy (D1B).
0FDD 0 Busy (D0B).

Status Register 0 (ST0)

Bit(s)Function
7Interrupt Code bit 1 (IC1).
6Interrupt Code bit 2 (IC2).
5Seek End (SE).
4Equipment Check (EC).
3Not Ready (NR).
2Head Address (HD).
1Unit Select 1 (US1).
0Unit Select 2 (US2).

Status Register 1 (ST1)

Bit(s)Function
7End of Cylinder (EN).
6Always zero.
5Data Error (DE).
4Over Run (OR).
3Always zero.
2No Data (ND).
1Not Writable (NW).
0Missing Address Mark (MA).

Status Register 2 (ST2)

Bit(s)Function
7Always zero.
6Control Mark (CM).
5Data Error in Data Field (DD).
4Wrong Cylinder (WC).
3Scan Equal Hit (SH).
2Scan Not Satisfied (SN).
1Bad Cylinder (BC).
0Missing Address Mark in Data Field (MD).

Status Register 3 (ST3)

Bit(s)Function
7Fault (FT).
6Write Protect (WP).
5Ready (RY).
4Track 0 (T0).
3Two Side (TS).
2Head Address (HD).
1Unit Select 1 (US1).
0Unit Select 0 (US0).

The Commands are as follows:

Read Data

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
5(SK) Enable Skip deleted data address mark.
40.
30.
21.
11.
00.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector to be read.

Byte 6: Number of bytes per sector.

Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Gap 3 Length.

Byte 9: DTL - Data Length to be read.

During execution data is transferred between the FDD and the CPU memory.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head read.

Byte 6: Final Sector read.

Byte 7: Number of bytes read.

Read Track

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
70.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
5(SK) Enable Skip deleted data address mark.
40.
30.
20.
11.
00.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector to be read.

Byte 6: Number of bytes per sector.

Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Gap 3 Length.

Byte 9: DTL - Data Length to be read.

During execution data is transferred between the FDD and the CPU memory. The FDC reads all data fields from index hole to EOT.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head read.

Byte 6: Final Sector read.

Byte 7: Number of bytes read.

Read Deleted Data

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
5(SK) Enable Skip deleted data address mark.
40.
31.
21.
10.
00.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector to be read.

Byte 6: Number of bytes per sector.

Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Gap 3 Length.

Byte 9: DTL - Data Length to be read.

During execution data is transferred between the FDD and the CPU memory.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table). Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head read.

Byte 6: Final Sector read.

Byte 7: Number of bytes read.

Read ID

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
70.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
50.
40.
31.
20.
11.
00.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

During execution the first correct ID information on the cylinder is stored in the Data Register.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Cylinder.

Byte 5: head.

Byte 6: Sector.

Byte 7: Number of bytes per sector.

Write Data

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
50.
40.
30.
21.
10.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

During execution data is transferred between the cpu memory and the FDD.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head written.

Byte 6: Final Sector written.

Byte 7: Number of bytes written.

Write Deleted Data

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
50.
40.
31.
20.
10.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector.

Byte 6: Number of bytes per sector.

Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Gap 3 Length.

Byte 9: DTL - Data Length to be written.

During execution data is transferred between the CPU memory and the FDD.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head written.

Byte 6: Final Sector written.

Byte 7: Number of bytes written.

Format Track

Command Phase: 6 bytes.

Byte 1: Command Code.

Bit(s)Function
70.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
50.
40.
31.
21.
10.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Number of bytes per sector.

Byte 4: Number of sectors per track.

Byte 5: GPL - Gap 3 Length.

Byte 6: D - Filler Byte.

During execution the FDC writes address headers to the entire track.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Cylinder number.

Byte 5: Head.

Byte 6: Sector.

Byte 7: Number of bytes per sector.

Scan Equal

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
5(SK) Enable Skip deleted data address mark.
41.
30.
20.
10.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector.

Byte 6: Number of bytes per sector.

Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Gap 3 Length.

Byte 9: STP - Step Factor: 1 = Contiguous: 2 = Alternate Sectors.

During execution data is transferred from the CPU memory and compared with data from the FDD.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head compared.

Byte 6: Final Sector compared.

Byte 7: Number of bytes compared.

Scan Low or Equal

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
5(SK) Enable Skip deleted data address mark.
41.
31.
20.
10.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector to be compared.

Byte 6: Number of bytes per sector.

Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Length of Gap 3.

Byte 9: STP - Step Factor: 1 = Contiguous: 2 = Alternate Sectors.

During execution data from the CPU memory is compared with data from the FDD.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head compared.

Byte 6: Final Sector compared.

Byte 7: Number of bytes compared.

Scan High or Equal

Command Phase: 9 bytes.

Byte 1: Command Code.

Bit(s)Function
7(MT) Multi-Track {Enable/Disable}.
6(FM) Select {MFM/FM} (Single/Dobule density) Mode.
5(SK) Enable Skip deleted data address mark.
41.
31.
21.
10.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Select (0 or 1).
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).

Byte 4: Head Number (as specified in the ID field).

Byte 5: Sector to be compared.

Byte 6: Number of bytes per sector.Byte 7: EOT - Final sector number on track.

Byte 8: GPL - Length of Gap 3.

Byte 9: STP - Step Factor: 1 = Contiguous: 2 = Alternate Sectors.

During execution data from the CPU memory is compared with data from the FDD.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).

Byte 2: ST1 - Status register 1 (See ST1 table).

Byte 3: ST2 - Status register 2 (See ST2 table).

Byte 4: Final Cylinder number.

Byte 5: Final head compared.

Byte 6: Final Sector compared.

Byte 7: Number of bytes compared.

Recalibrate

Command Phase: 2 bytes.

Byte 1: Command Code.

Bit(s)Function
70.
60.
50.
40.
30.
21.
11.
01.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
20.
1US1.
0US0 - Unit Select (0 or 1).

During execution phase, the Head is retracted to Track zero.

No status information is returned during the result phase.

Sense Interrupt Status

Command Phase: 1 byte.

Byte 1: Command Code = 08h.

The Result phase returns two bytes:

Byte 1: ST0 - Status Register 0.

Byte 2: PCN - Present Cylinder Number.

Specify

Command Phase: 3 bytes.

Byte 1: Command Code = 03h.

Byte 2: SRT/HUT - Step Rate Time (4 MS bits - in 1 ms increments)/Head Unload Time (4 LS bits - in 16 ms increments).

Byte 3: HLT/ND - Head Load Time (Bits 1 to 7 - in 2 ms increments)/Non-DMA Mode (Bit 0).

Seek

Command Phase: 3 bytes.

Byte 1: Command Code = 0Fh.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
2HD - Head Number.
1US1.
0US0 - Unit Select (0 or 1).

Byte 3: New Cylinder Number.

During execution phase, the Head is positioned to the specified Cylinder.

No status information is returned during the result phase.

Sense Drive Status

Command Phase: 2 bytes.

Byte 1: Command Code = 04h.

Byte 2: Head and Unit select.

Bit(s)Function
7-3Don't Care.
20.
1US1.
0US0 - Unit Select (0 or 1).

Result phase: 1 byte.

Byte 1: ST3 - Status Register 3.

Invalid Opcodes

All command codes not listed above are considered invalid. When an invalid code is encountered the FDC returns the ST0 register with the MS bit (Invalid Opcode bit) set.


Section 2 Index Appendices