AMSTRAD PC1640 TECHNICAL MANUAL

1.0 Introduction

This manual provides a comprehensive description of the AMSTRAD PC1640 hardware and firmware. General information about the PC1640, GEM Desktop and the delivered operating system software is contained in the AMSTRAD PC1640 USER GUIDE. This manual is intended to satisfy the needs of advanced developers who must have access to the various resources available within the PC1640.

Note that all address constants in this document are hexadecimal. In addition hexadecimal quantities are noted with small letter 'h' terminator to denote that they are in hexadecimal form. Address quantities are not usually annotated this way since they are clearly hexadecimal. Values are presented in hexadecimal form when they are logically bit oriented quantities rather than of purely numerical significance.

1.1 Central Processing Unit (CPU)

The CPU is an 8086-2 microprocessor with 1 Megabyte memory addressing capability (See Figure 1), running at a clock frequency of 8MHz. The CPU is connected to an on-board 16-bit system memory bus requiring four 125nS timing cycles (T-States) per access resulting in a 500nS memory cycle for 16-bit memory. The CPU is also connected on an on-board 8 bit I/O and memory peripheral bus with a 4 MHz clock, which in turn connects to an external expansion bus. Operations on the 8-bit bus automatically incur 125nS wait states as follows:

The CPU is configured to run in maximum mode and the instruction set may be optionally extended by the addition of an 8087-2 Numeric Data Coprocessor. The 8087 BUSY output is connected directly to the 8086 NOT TEST input.

1.2 MEMORY LAYOUT

The main board memory consists of 640K bytes of system RAM with parity checking and 16K bytes of system ROM without parity checking.

The 640K byte user RAM starts at CPU memory address 00000 and extends to 9FFFF.

The 128K byte address space from A0000 to BFFFF is reserved for video regeneration buffers, and is not used by CPU programs. The PC1640 Internal Graphics Adapter (IGA) uses the full 128K byte range or segments of this memory range depending on the display mode (see section 2, Video I/O Int 16). External display adapters also use this memory address range for their display buffers.

The 192K byte address space from C0000 to EFFFF is reserved for external expansion ROM address space. When the Internal Graphics Adapter is enabled, it uses the space from C0000 to C1FFF for its bios (executable) code and the area from C2000 to C7FFF for its fonts. The optional Hard Disk controller uses the range from C8000 to C9FFF. Additional hard disk controllers may also use the area from CA000 to CD000. The PC1640 test board uses the ROM area from E0000 to E7FFF.

The 16K byte system ROM is at FC000 to FFFFF and contains the Resident Operating System (ROS) firmware. The 48K byte address range from F0000 to FBFFF is reserved for ROM space expansion. The 16K byte ROS area address bits are partially decoded such that the ROS ROM repeats four times in the F0000 to FFFFF address range.

1.3 MAIN BOARD I/O CHANNELS

The interfaces on the main board occupy the 8086 I/O addresses as follows:

1.4 EXPANSION BUS I/O CHANNELS

The 8086 CPU I/O addresses on the expansion bus are as follows:

I/O address above 03FFh, if accessed, wrap around and are mapped onto the range 0000h-03FFh.

External cluster controllers at 0790h-0793h, 0B90h-0B93h, 1390h-1393h and 2390h-2393h wrap around to I/O addresses 0390h-0393h respectively.

1.5 Direct Memory Access (DMA)

The Amstrad PC 1640 supports four DMA channels on the system board, using an 8237-4 DMA controller and programmable page registers to extend its addressing range from 64k bytes to the full 1M byte processor address range. Each channel is able to transfer data in blocks of up to a maximum of 64K bytes within a page. The DMA channels are for 8-bit data transfers between (8-bit) I/O devices and 8-bit or 16-bit memory.

In peripheral (slave) mode, CPU I/O address lines A0 - A3 are connected conventionally so that 16 command codes appear in the order described in the 8237 data sheets (See section 3.5).

The DMA controller CLK is driven at 4MHz (+/- 0.1%). In master mode during DMA transfers on channels 1,2 and 3, one wait state is added resulting in a five-clock DMA bus cycle of 1.25uS. Channel 0 transfers have a four-clock bus cycle of 1uS.

The DMA channel request signals are as follows:

1.5.1 DMA Page Registers

DMA channels 1, 2 and 3 can address the entire 1M byte addressing range of the CPU through the use of their associated DMA page registers. There are three DMA registers, one each for channels 1 through 3. Each page register defines for its channel which one of sixteen 64K byte pages in the 1M byte address range DMA transfers are to occur. The page registers are static so that modulo 64K byte addressing occurs at page boundaries.

The DMA page register bit assignments are as follows:

1.5.2 DMA Initialisation

Following a reset, system (ROS) initialisation firmware (in the ROS) sets up the 8237 DMA controller for channel 0 (dynamic refresh) operation as follows:

After power-up or system reset the DMA page registers are undefined and are initialised to zero by the ROS firmware and all 8237 internal locations for channels 1-3 are initialised to a state comparable to the channel zero initialisation above.

Following industry compatibility, memory to memory DMA is not supported on the PC1640. It is prohibited due to timing considerations.

1.6 System Interrupts

Nine levels of hardware interrupt are provided for in the system by the CPU Non Maskable Interrupt (NMI) and by an 8259A-2 Interrupt Controller. All levels including NMI, are maskable under software control.

CPU I/O address line A0 is connected conventionally so that the command codes appear in the order described in the 8259 data sheets. The SP/EN pin is tied high signifying that the device is to be hardware un-buffered and designated as a master, not a slave.

1.6.1 Interrupt Levels

The interrupt levels are assigned as follows:

The system (ROS) firmware initialises the 8259 address bits such that IRQ0 through IRQ7 appear in the CPU interrupt vector space at interrupts 8 through 15 repectively. NMI appears at CPU interrupt vector 2.

1.6.2 Interrupt Controller Initialisation

Following a reset, the initialisation firmware in the ROS sets the 8259 Interrupt Controller to operate as follows:

8086 system, Single (not cascaded),
Normal fully nested (not special),
Edge-triggered,
Buffered mode - slave,
Normal EOI (not auto),
Fixed priority - level 0 highest, level 7 lowest.

The system (ROS) firmware initialises the 8259 address bits such that IRQ0 through IRQ7 appear in the CPU interrupt vector space at interrupts 8 through 15 respectrively. NMI is configured to CPU interrupt vector 2.

1.6.3 NMI Mask Control

The NMI Mask Control is a write only register at I/O address 0A0h and allows the CPU non-maskable interrupt (NMI) input to be enabled or disabled by software. The Bit assignments are as follows:

Following a reset NMI is disabled.

NMI can be connected to the 8087 NDP, the on-board memory parity check circuit, and the expansion bus I/OCHCK (I/O Channel Check).

1.7 Programmable Interval Timers

Three programmable timer/counters are provided at I/O Addresses 040 - 043 by an 8253 Programmable Interval Timer (PIT) device. They are defined as follows:

1.7.1 Timer Configuration

The 8253 timers are configured as follows:

1.7.2 Counter 1 initialisation

Following a reset, the system initialisation firmware in the ROS programs the 8253 PIT for counter 1 (dynamic ram refresh) operation as a rate generator producing a signal with a period of 15.13 uS. There are no restrictions requiring the initialisation and programming of counters 0 and 2.

1.8 System Status and Control

Two system status input channels and four output channels are provided on-board. Ports A, B and C emulate a pre-programmed 8255 PPI device. They are located in the I/O address space in the range 060h - 06Fh. Port B is programmed for control output, Port A is programmed either for Status-1 input or for receiving data from the keyboard, and Port C is programmed for Status-2 input.

Ports A, B and C emulate an 8255 PPI that has been set up as follows:

Unlike an 8255, power-up and reset do not affect this configuration.

1.8.1 Port B - System Control

The System Control channel is located at I/O Address 061h. Its bit assignment is as follows:

When bit 7 is set high, Status-1 data is enabled on Port A, the keyboard data path and keyboard interrupts are disabled. When bit 7 is set low, keyboard input data is enabled on port A, the keyboard data path and keyboard interrupts are enabled. Applications software which sets PB7 must restore it to the cleared state else the keyboard may be rendered inoperable.

The keyboard interface operates as follows: Each incoming keycode is latched on-board, causing a keyboard interrupt (on level 1). While the interrupt remains pending, the incoming keyboard data signal is forced low as an acknowledgement to the keyboard that the keycode has been received. As soon as the interrupt has been cleared, the keyboard may use the Data signal to transmit the next keycode.

PB5 when set prevents an external parity error (ie. an I/OCHCK condition on the expansion bus) from causing NMI, even if NMI is unmasked. When NMI has been triggered and latched it may be cleared by pulsing PB5 (if the external device has removed its I/OCHCK signal).

PB2 when set enables the reading of the four LS bits of the RAM fitted indicator on Port C. When PB2 is clear the top (MS) bit of the RAM fitted indicator is read (see 1.8.3).

PB1 may be toggled to drive the speaker with a corresponding pulse train. The speaker may also be driven by a wave form from the 8253 PIT OUT2 output (simultaneously with PB1).

PB0 may be toggled to drive the 8253 gate input, hence modulate counter 2operations and therefore driving the speaker which may all be performed simultaneously to create various audio effects.

1.8.2 Port A - Status-1 Input/Keyboard Code

Port A is a read only location located at I/O Address 060h. The bit assignments for Port A are as follows:

When Port B, Bit 7 (PB7) is set to high, reading Port A loads Status-1. When PB7 is set low, reading Port A loads keyboard data.

The Default Display Mode bits (DDM1, DDM0) are set up by the ROS during system initialisation as follows:

When the Internal Graphics Adapter (IGA) is enabled then switches 1 - 5 determine what the default display mode is and whether the IGA is the primary or the secondary adapter. See section 1.22 for these details.

When the Internal Graphics Adapter (IGA) is disabled then the ROS uses the position of display selector switches SW6, SW7 and SW10 to determine the default display mode.

When an EGA or another adapter is installed then its particular User's/Hardware manual is the best guide to its display modes or other features.

Following a reset, the ROS then sets the initial video state is based on the DDM value. Section 2.3.7 gives additional details of the ROS Video Mode settings.

1.8.3 Port C - Status-2 Input

Port C is a read only location located at I/O Address 062h. Its bit assignments are as follows:

PC7 is forced to the zero state when on-board system RAM parity checking is disabled by PB4.

When the I/OCHCK condition (external parity error) from the expansion bus is disabled from causing NMI (by PB5 set high), PC6 reflects the state of the I/OCHCK input else it reflects the latched state of I/OCHCK.

The value of RAM4-RAM0 denotes the amount of system RAM fitted to the system as follows:

Since the PC1640 comes with 640K of RAM fitted the expected value should always be 640K bytes. Any other value indicates an installed memory configuration error.

See section 1.8.1 for the Control Port B setting for reading RAM fitted segment bits.

1.8.4 Write System Status-1

The Write System Status-1 register (WSS1) is a write only register at I/O Address 064h and is initialised by the Resident Operating System (ROS) firmware based on values obtained from configuration switches 4 and 5. It is used in conjunction with the 8255 PPI Port A emulation. The bit assignments are as follows:

1.8.5 Write System Status-2

The Write System Status-2 register is a write only register at I/O Address 065h and is initialised by the Resident Operating System (ROS) firmware based on the memory size check perfomed during Power On Self Test. It is used in conjunction with the 8255 PPI Port C emulation. The bit assignments are as follows:

Since the PC1640 comes with 640K on the main board the expected value of PC3 - PC0 is binary 10010.

1.8.6 System Reset

Any write access to I/O Address 066h regardless of the value written will cause the hardware to generate an immediate 512uS system reset and pulse the reset line on the expansion bus. The contents of the on-board system RAM is preserved following a system reset.

1.9 Real Time Clock

A HD146818 Real Time Clock plus RAM device is installed and backed up by a set of four non-rechargable size AA batteries. The clock device provides a time of day clock with alarm, a one hundred year calendar, a programmable periodic interrupt, and 50 bytes of static RAM. The static RAM is called the Non-Volatile RAM (NVR) and used to store system configuration data such as number of disk drives, memory size, serial I/O parameters, and default VDU screen mode. The ROS firmware maintains a checksum of the NVR and will reset the configuration data to 1sensible values1 during startup whenever the checksum value is incorrect (thus destroying your actual configuration). Even though direct hardware access to the NVR is possible it is recommended that the programs make use of the ROS Enhanced Function Interrupt (Interrupt 21) to access the NVR because these properly maintain the NVR checksum value.

When system power is off and the 146818 is on battery backup power, the functions which remain active are the clock and the retention of RAM data. No battery power is used while the system power is on.

The input crystal oscillator runs at 32.768 KHz and the 146818 interrupt request is connected to the 8259 system interrupt controller on level 2 (which is also available on the expansion bus). The 146818 power-sense input PS is connected to a battery condition sensor. When the backup battery voltage is sufficiently low, the VRT bit in register D becomes set indicating that the time, the calendar and the NVR data are no longer valid. When this condition is noted during startup, the firmware outputs the message "Please fit new batteries" and resets the NVR to default values (See section 2.4).

All the features described in the 146818 data sheet are available with the exceptions that the CKOUT (clock output) and SQW (square wave output) pins are not connected on the main board.

Writing or reading the NVR involves a two step sequence for each byte that is accessed. The RTC Address channel (I/O Address 070) is first loaded with the NVR location to be accessed. Then the RTC Data channel (I/O Address 071) is either written or read to complete the I/O operation. This facility should be used with caution in order to avoid disturbing the system configuration data.

1.10 Parallel Printer Port

The printer port provides an interface for driving 8-bit and 7-bit Centronics compatible printers. The timing of the signals to the printer is under direct software control. There is a read/write control latch for sending control signals to the printer, an unlatched read-only printer status channel, and a read/write data latch for sending printer data.

In addition the printer control latch can be read to obtain system type and switch information.

1.10.1 Printer Data Latch

The printer data latch is a read/write record at I/O address 378 and its layout is as follows:

The contents of the data latch are undefined following a power-up or system reset.

1.10.2 Printer Control Latch

The printer control latch is a read/write record at I/O address 37A and its layout is as follows:

Bit D7 is a read-only bit which reflects the state of switch 7 (at the back of the machine) and returns a logic "1" when the switch is in the "on" position and a logic "0" if in the the "off" position.

Bit D6 is a read-only bit which reflects the state of switch 6 (at the back of the machine) and returns a logic "1" when the switch is in the "on" position and a logic "0" if in the the "off" position.

Bit D5 is the option (OPT) bit and can return one of three different pieces of information. Although not documented as such on the PC1512, Bit D5 was always a "1", however on the PC1640 it will always be a zero if immediately prior to the read of channel 037Ah the software performs an I/O read of an I/O channel implemented on the PC1512 main board, having address line A7 high (for example, the CGA channels). This is a simple test for software to detect whether it is running on a PC1512 or a PC1640. A PC1512 will give a 1, whereas a PC1640 will give a 0.

In addition to being a test of machine type the OPT bit, D5, can also reflect the state of either SW9 or SW10. The OPT bit will reflect the state of switch SW9 by an I/O read operation to an I/O channel not implemented on the main board and having address lines A14 and A7 both low (for example channel 0278h) immediately prior to the reading of channel 037Ah. The OPT bit is set to the state of switch SW10 by an I/O read operation to an I/O channel not implemented on the main board having address lines A14 high and A7 low (for example channel 4278h). Software testing OPT bit should disable interrupts before the initial (dummy) channel read and the I/O read of channel 037A in order to avoid additional (interrupt based) I/O operations between the setting and the testing of the information read back in the OPT bit. For switches SW9 and SW10, a logic "1" is returned when the switch is on the "on" position and a logic "0" if the switch is in the "off" position.

When Interrupt on ACK is enabled an incoming Printer Acknowledge condition will cause a system interrupt on level 7 (which is also available on the expansion bus).

If the printer control lines normally driven via latched bits D0 - D3 are driven externally, the data read on input to this channel will be the logical OR of the latched bits and the externally driven bits, e.g. If a data bit is false and the corresponding cable bit is driven true by the external driver, the bit input will be true.

Following power-up or system reset, the control latch contents assume reset conditions as shown.

Note that this is a general purpose printer interface and that not all printers require all the control signals, hence the provision for non-standard printers to be able to drive some of the control signals as inputs to the main board. The timing requirements on Centronics compatible printers generally specify that data must be present at 1uS before the strobe is made active, and must remain valid for at least 1uS after strobe goes inactive. The strobe duration must be between 1uS and 500 uS. Printer Busy status can be inspected as soon as the strobe is inactive in order to determine when more data can be sent.

1.10.3 Printer Status Channel

The Printer Status Channel is a read only register at I/O Address 0379h. Its layout is as follows:

LK1 - LK3 are general purpose factory installed option links on the main board which are used by the system ROM Operating System (ROS) firmware to distinguish national variant machine configurations. The ROS will produce its sign-on message and error messages in one of seven languages. The first seven states (0 - 6) are used for language variants and the eighth (7) state is used extended diagnostic mode testing (See section section 2.2). Since the link state is inverted, the value obtained from the lower three bits of the printer port must be exclusive or'ed (XOR) with 1's to obtain the language number.

Note that this is a general purpose printer interface and that not all printers implement all the status lines, nor do they all attach the same meanings to the error conditions.

Printer Busy normally indicates that a printer cannot receive data, for example during data entry, printing, when offline, or during a printer error condition.

Printer Acknowledge, if implemented is generally asserted by a printer to indicate that data has been received and the printer is ready to receive the next data. Note that Printer Acknowledge (ACK) can also be set to cause interrupts (See 1.10.3).

Section 1.14 contains the printer connector pin assignments.

1.11 The Internal Graphics Adapter.

The Internal Graphics Adapter (IGA) is a gate array on the main board which provides either an Extended Graphics Adapter (EGA) mode, or a Color Graphics Adapter (CGA) mode or a Monochrome Display Adapter (MDA) mode. Additional Hercules monochrome adapter modes and Plantronics (Color) adapter functions are also supported.

The video screen memory (or regeneration buffer) is the 128K byte range from A0000 to BFFFF and its configuration varies depending on the selected display mode. The regeneration buffer origin (ie the starting address) may be configured to either A0000, B0000 or B8000 with sizes varying from 2K bytes to 32K bytes. (See 1.11.2.5).

When an Extended Color (PC-ECD) Display is fitted the IGA is capable of displaying up to 64 different colors in EGA mode with a resolution of 640 dots x 350 lines. The CGA and Plantronics display modes supports 16 colors (for Extended Color Displays and standard Color Displays) with a resolution of up to 640 dots by 200 lines.

For the PC-MD monochrome display, the IGA supports black and white text in normal, intense, blink, or underline with a resolution of 720 by 350 in text modes. The maximum monochrome Graphics resolution is 640 x 350 or 720 x 348 resolution graphics for Hercules compatible monochrome.

For color systems, when an initial mode change is set up via the ROM BIOS, a set of sixteen color palette registers are loaded with standard values such that a standard IRGB color selection is available for sixteen total colors available on the display. The color attribute fields (discussed later) and the color plane selections relate to the standard sixteen color palette format as follows:

Note that the Extended color display (PC-ECD) supports 64 colors using a 6-wire rgbRGB color scheme (where the capital letters represent 2/3 intensity primary color signals and the small letters represent 1/3 intensity secondary color signals). Since each of the sixteen palette registers is a 6-bit register with the bits representing rgbRGB (MSB through LSB respectively) only 16 of 64 colors can be displayed on the screen at any one time.

1.11.1.1 Color Alpha Display

In Color mode, two Alpha modes are available: either (medium resolution) 40 characters by 25 rows or (high resolution) 80 characters by 25 rows. The display RAM requirement is 2K bytes and 4K bytes of display RAM for 40 and 80 column modes respectively. The display regeneration buffer is from B8000h to BBFFFh for these modes and the display ROM bios supports up to 8 or 4 separate display pages for 40 and 80 column modes respectively.

The character set is formed by a RAM loadable character generator and for 200 line resolution systems, each of the 256 characters is made up of a 8 by 8 pixel matrix.

When an Extended Color Display (PC-ECD) is being used in full 350 line resolution, the 40 and 80 column text modes are still supported but the character generator is programmed differently and a 8 by 14 pixel matrix is used. The display RAM mapping and regen buffer origin and size requirements are exactly the same as the 200 line display modes.

The starting address in the display RAM is programmed via the CRT (Cathode Ray Tube) Controller (CRTC). The starting address is on an even address boundary and it addresses the first (leftmost) character position in the top row of the display. The CRTC starting address register is a 16-bit register and it specifies the offset in two byte pairs from the display mode origin. This means for each change of one in the CRTC starting address register, the next even address is selected in the display RAM as the current regeneration buffer origin.

In order to display a single character, two bytes of display RAM are required, and for each pair of display RAM bytes, the even address is for the character code and the odd address is for the attribute byte. Subsequent characters are displayed along the row from left to right. When the end of a row is reached the next pair in the display RAM appears in the first character position of the next row down. Appendix 8 gives the 256 character codes and their respective default character representations. Note that the ROM bios for EGA mode supports reprogramming the character generator with user supplied character matrices.

The attribute byte allows a choice of either 16 foreground and 8 background colors per character, plus blinking, or a choice of 16 colors for both foreground and background without blinking. In CGA mode, the display border may be programmed for any one of the 16 colors.

The attribute byte for each is as follows:

Bit 7, the Intensity or Enable Blink Bit, changes function based the Mode Control Register. In EGA mode, Mode Control Register (I/O address 03C0h, index 10), Bit 3 selects between Intensity or Blink in standard alphanumeric display modes. For CGA compatible mode, Mode control Register (I/O address 03D8h) bit 5 selects between Intensity or Blink.

In EGA mode bit 3, the foreground intensity bit, can be used as an alternate character map select bit to obtain up to 512 displayable characters for a given screen. The extended character map option is explained in section 1.11.3, IGA Extended Graphics Mode Registers, in the section which deals with the Character Map Select Register which is contained in the sequencer logic.

Note that in EGA mode, the bit positions listing IRGB actually selects one of the 16 paletter registers and depending on the contents of the selected palette register the (extended six-wire) color signals are produced accordingly. If the palette registers are left unchanged from the initial values loaded at mode change the color selections will be given the sixteen standard colors listed in the color table at the beginning of this section. The table below gives the palette register settings which produce the standard 16 color palette.

The small (lower case) letters represent the secondary colors at 1/3 intensity each and the big (upper case) letters represent the primary colors at 2/3 intensity each.

1.11.1.2 Monochrome Alpha Display

When driving a Monochrome (PC-MD) Display, there is only one Alpha mode available, 80 characters by 25 rows with a resolution of 720 dots by 350 lines. The display RAM requirement is in 4K increments in display regeneration buffer area from B0000h to B7FFFh. The display ROM bios supports up to 8 separate display pages. Buffer 0 is from B0000 to B0F9F, buffer 1 is from B1000 to B1F9F with the remaining 6 buffers starting on even 1000h boundaries to B7000.

In EGA mode the character set is formed by a RAM loadable character generator and each of the 256 characters is made up of a 9 by 14 pixel matrix.

The CRTC Starting Address is programmed in the same way as when in color modes and the two byte character and attribute pairs are arranged in the display RAM just as in the color modes. The attribute byte, however assumes different functions from the color attributes since there are no IRGB signals sent to the monitor, but Video & Intensity are produced. The monochrome attribute byte is as follows:

Bit 7, the Background Intensity/Blink Enable (B/I) Bit, changes function based the Mode control register. In EGA mode, Mode Control Register (I/O address 03C0h, index 10), Bit 3 selects between Intense background when inverted or Blinking. For MDA compatible mode, Mode control Register (I/O address 03B8h) Bit 5 selects between Intensity or Blink Functions. The Hercules modes follow the same scheme in text mode.

Bit 3 is the foreground intensity bit and controls the intensity when not in inverse video or blanked. It is also necessary to turn the contrast down on the PC-MD display in order to observe the difference in video levels.

1.11.2.1 Colour Graphics Display

PC-CD (Standard Color Display) systems support 200 scan lines with a choice of two graphics resolutions, either 320 pixels per scan line with four colors per pixel or 640 pixels per scan line with a two colors and these are termed 'CGA' compatible modes. Additional sixteen color (EGA) modes are also available in the above two resolutions. In the CGA compatible modes, the regeneration buffer for the 320x200 4-color mode and 640x200 2-color mode starts at B8000 and requires 16K bytes per display page. The IGA ROM BIOS supports either 8 or 4 display buffer pages for the 320 or 640 resolution modes respectively.

For EGA 16 color modes, the regen buffer starts at A0000 and is divided into four 64K byte planes, one each for the Blue, Green, Red and Intensity bits. Each plane may be individually read from or written to by the CPU, and two or more planes may be selected by the CPU for writing simultaneously with the same data. Individual data bits can be either enabled or disabled during CPU writes to the graphics memory. The section on registers (1.11.3 below) will explain the methods available for graphics control.

PC-ECD (Extended Color Display) systems support the 200 line resolution modes described above with an additional 16 or 64 color, 640x350 resolution mode. For the high resolution (350 line) mode the regen buffer starts at A0000 and requires 28K bytes per display page. The IGA ROM BIOS supports 2 display pages for the 350 line mode. The 16 color selection is by way of four color planes as described above. The 16 of 64 possible colors is achieved by reprogramming the palette registers introduced in the color text description.

1.11.2.2 Low Resolution (320 x 200) Graphics

In Low Resolution Graphics Mode, the display memory for one scan line (320 pixels) consists of 80 bytes. Each pixel requires two bits so that four pixels are specified by each byte. The leftmost pixel is contained in the two MS bits of the byte and the two bit pairs for the remaining pixels follow on logically from left to right. The two bit field for each pixel specifies one of four colors and can be in one of three palettes as follows:

The display regeneration buffer for medium resolution graphics modes is mapped a split buffer configuration with the even scan lines (0, 2, 4, ... 198) contained in the graphics memory space from B8000 to B9F3F and the odd scan lines (1, 3, 5, ... 199) in the memory address range from BA000 to BBF3F. The memory map is as follows:

The mapping of a byte of graphics RAM in low resolution mode is as follows:

1.11.2.3 Medium Resolution (640 x 200) Graphics Mode

In Medium Resolution Graphics Mode, the display memory for for one scan line consists of 80 bytes. Each pixel requires one bits so that eight pixels are specified by each byte. The leftmost pixel is contained in the MS bit of the byte and the remaining pixels follow from left to right. In high resolution mode the two colors are either black (pixel bit off) or pixel bit on with video in one of the 16 colors as selected by a foreground palette register.

One byte of graphics RAM in medium resolution graphics is as follows:

The address mapping of the scan lines in display RAM for high resolution graphics is the split buffer configuration depicted for medium resolution mode. - All (100) even scan lines from B8000 to B9F3F followed by all (100) odd scan lines from BA000 to BBF3F.

1.11.2.4 High Resolution (640 x 350) Graphics Mode

In High Resolution Graphics Mode, the display memory required for each scan line is 80 bytes which is the same as the 640 pixel scan lines of the medium resolution mode. The major difference is that there are 350 scan lines which are mapped into a contiguous block of display memory starting at A0000 and extending to AFFFF. The IGA ROM BIOS supports two display pages by reprogramming the CRTC starting address register. Page 0 is from A0000 to A6D5F and page 1 is from A8000 to AED5F.

In high resolution mode the display RAM mapping is very straight forward, the 350 display lines are in contiguous 80 byte blocks in the regeneration buffer. The internal pixel to RAM bit mapping is the same as depicted above for medium resolution graphics mode.

This display graphics mapping applies for both EGA Monochrome (BIOS Mode 15) and for EGA High Resolution Color (BIOS mode 16) graphics. The Hercules 720 by 348 graphics mapping is not so straightforward and requires a graphics map which is segmented into four pieces. This mapping scheme is covered in section 1.11.7 with the Hercules Mode control registers.

1.11.2.5 IGA BIOS Modes

The IGA BIOS sets up the hardware to support twelve different modes for the various displays available on the PC1640 range. The following table gives the modes supported by the BIOS ROM. Mode numbers between 8 & 12 are dummy mode numbers for other graphics adapters not supported by the IGA ROM BIOS.

The Regeneration Buffer Origin is stated in hexadecimal notation since it is an address quantity. All other values are in decimal notation in order to give a numerical perspective to the quantitites.

The IGA ROM BIOS supports multiple display pages and can be called to select an alternate page. The default (base page) upon initial mode selection is always zero and it begins at the origin address. The successive pages are located higher by the page size increment in the table. The equation for page origin is: Page Origin = Regen Origin + (Page Number - Page Size). Since the 'Page Size' quantity is a pure binary multiple it becomes a shift factor for the selected page number. Page are numbered from 0 to n-1 where 'n' is the number of pages available.

The maximum display pages for modes 0 and 1 is listed to be 16 for each. While this is true from a hardware point of view, the IGA ROM BIOS only supports the first eight and the additional pages though accessible via direct access to the memory map, the video character output routines in the ROM BIOS will not correctly access alternate page numbers 8 - 15.

1.11.3 IGA Control Registers

The control registers available in the IGA are somewhat complex but allow a versatile alphanumerics (text) and graphics display environment. The PC1640 ROM Operating System (ROS) and the IGA ROM BIOS allow a simplified set of software interfaces to this hardware and this should be the preferred method of implementing programs with some measure of transportablility to future hardware which may not be compatible with this environment at the hardware level.

Special IGA Registers

There are three special registers which control the overall IGA operational mode and setup characteristics of these modes. The IGA ROM BIOS and the DISPLAY utility program supplied with the PC1640 are the usual programs which sets up these registers. The IGA does not auto-switch, that is, it will stay in a selected hardware emulation mode until some program such as the DISPLAY utility manipulates the control registers. In addition applications programs with drivers for particular hardware will use these registers for their control purposes. The Special IGA Registers are as follows:

Extended Mode Control Register

The IGA Extended Mode Control Register controls the overall operational mode of the IGA such that it can be in EGA, CGA, MDA, Hercules or Plantronics emulation modes. The Extended mode control register is a write only 8-bit register located at I/O address 3DB/3BB and it can only be written to after two successive I/O reads of address 3D8/3B8. This is a protection feature which prevents accidental modifications from taking place. In order to determine whether to use I/O addresses 3B8/3BB or 3D8/3DB (Mono or Color addresses) it is necessary to know whether the system is configured in monochrome or color mode. The standard method for doing this is to use the system ROS's CRTC I/O address pointer located at RAM address 00463. This word (16-bit) will contain either 3B4 or 3D4 depending whether the system is in monochrome mode or color display mode respectively.

The format of the IGA Extended Mode Control register is as follows:

Bit 7 when set forces negative polarity of vertical sync and also blanks the screen border.

Bit 6 when set enables the 6845 compatible modes, CGA, Monochrome, Hercules and Plantronics modes.

Bit 5 when set locks out the Palette registers and the Overscan register.

Bit 4 when set prevents modification of the CRT Controller registers which determine sync signal timing.

Bit 3 when set provides an additional character set option of four 8Kb character sets from plane 3. (See page 40 for additional details.)

Bit 2 when set disables the screen blanking in the CGA Color Alpha mode.

Bit 1 when set enables the 132 Character Mode.

Bit 0 when set enables color simulation modes.

Hercules Mode Register

The Hercules Mode Register is active when Hercules Monochrome Graphics is enabled and is a write only register at I/O address 3BF. It controls the configuration of the graphics memory map and protects against accidental setting of the graphics mode bits in the mode control port at 3B8. The layout of this register is as follows:

Since Hercules mode resembles MDA mode but with graphics extensions, applications software built for the MDA may inadvertently set the Hercules graphics control bits. This register prevents such accidents by forcing the respective bits to zero so that text mode is maintained and the display buffer remains at B0000.

Plantronics Mode Register

Plantronics mode is an additional color mode which allows CGA-like color but with extensions for four colors in 640x200 resolution and 16 colors in 320x200 resolution through use of an additional color plane residing in the BC000 memory range. The Plantronics Mode Register (PLR) is a write only register located at I/O address 3DD. Its format is as follows:

Bit 6 when clear enables color plane 0 to start at B8000 and color plane 1 to start at BC000. Setting bit 6 swaps the two plane's starting addresses so that color plane 0 starts at BC000 and color plane 1 starts at B8000. Each color plane is 16K bytes in length.

The Extended color palettes enable combinations of bits set is planes 0 and 1 to select one of four different colors for 640 dot resolution or one of 16 colors in 320 dot resolution modes.

When both bits 4 and 5 are cleared standard CGA mode is enabled. When both bits 4 and 5 are set together then bit 4 overrides bit 5 but it is recommended that either bit 4 or bit 5 be set individually else unusual effects may occur. Bit 6 has no effect unless one of bit 4 or bit 5 is set.

EGA Mode Compatible Registers

There are sixty-five EGA Mode compatible registers which control the characteristics of the Extended Graphics Environment. These registers are are grouped into five logical groups, EGC (External) Control, Attribute Controller, Sequencer, Graphics Controller, and the CRTC Controller. They are listed in their respective groupings below:

The CRT Controller registers will either reside in the 3B- range for monochrome display mode or in the 3D- range for color display modes. This variable address selection is by way of bit 0 in the EGC Control register at I/O address 3C2.

EGC External Control Registers

The EGC External Control registers comprise a group of two registers which enable reading of information such as switches and enable a number of other hardware setup functions.

EGC Control Register (3C2 Out)

The EGC Control Register is a write only register which resides at I/O address 3C2. Its format is as follows.

Bit 7 = '0' for positive VSYNC polarity, and bit 7 = '1' for negative VSYNC polarity.

Bit 6 = '0' for positive HSYNC polarity, and bit 6 = '1' for negative HSYNC polarity.

Bit 5 enables the selection of an alternate 64K display RAM for text modes (BIOS Modes 0 - 3 and 7). Bit 5 = '0' for the default (Low) 64K Text Page and bit 5 = '1' for the alternate (High) 64K Text Page select.

Bit 4 when set disables internal video and enables a data path for video from an external (Features) connector. However no such connector is provided on the PC1640 main board IGA. Bit 4 should always be written as zero.

Bits 2 and 3 form a two-bit field which selects one of two clock rates. When both bits are zero (bit 3 = bit 2 = '0') then 14MHz clock is used as the clock source and when bit 3 is zero and bit 2 is one (bit 3 = '0', bit 2 = '1') then 16MHz is used as the IGA clock source. The other two combinations are not valid for the PC1640. In addition to selecting the clock rate Bits 2 and 3 form a two bit field for reading the system board switches 1 - 4 and comprise a ones complement switch select field (See EGC Status - page 35).

Bit 1 = '0' disables CPU access to the display RAM and bit 1 = '1' enables CPU access to the display RAM.

Bit 0 maps the CRTC for Monochrome I/O addressing or Color I/O addressing. When bit 0 = '0' the CRTC resides at 3B4 & 3B5 for monochrome mode and when bit 0 = '1' the CRTC resides at 3D4 & 3D5 for color mode. The Status Port register is also remapped from I/O address 3BA in monochrome mode to I/O address 3DA in color mode.

EGC Status Register (3C2 In)

The EGC Status Register is a read only register which resides at I/O address 3C2. Its format is as follows.

Bit 7 = '1' when the VSYNC is waiting and bit 7 = '0' when VSYNC interrupt request has been cleared or is inactive.

Bit 4 works in conjunction with bits 2 and 3 of the EGC Control register to form a switch sense selector. When bit 4 = '0' the selected switch (1 - 4) is closed. The following tables gives the switch select settings.

The IGA ROM BIOS reads these switches during the Power On Self Test (POST) initialization phase and deposits the switch complement value in the system storage location 0:488. Bits 0 - 3 correspond to the ones-complement of switches 1 - 4 respectively. The four MS bits of location 0:488 will always be ones on the PC1640.

Attribute Controller Registers

The Attribute Controller is a hardware grouping within the Extended graphics Controller which provides for color management. The major components of this section of logic are the palette registers which allow for the selection of 16 of 64 colors at any one time.

Attribute Controller Address Register

The Attribute Controller Address Register is a write only register which at I/O address 3C0h. When written to, its contents represent an index into the Attribute Controller register set which also resides at I/O address 3C0. The processor must first output the Index value followed immediately by the register value to be written. Any divergence from this two byte output scheme will cause following operations to confuse Index and data values.

Palette Registers (00h - 0Fh)

The sixteen Palette Registers reside at index positions 00h through 0Fh in the attribute controller and the bit assignments for each is as follows:

The Palette registers are each six bits wide and the bits are arranged such that the output color signals will correspond (from MS to LS bits) in the order rgbRGB. The major point to note is that secondary green and Intensity are on the same video output pins. The IGA ROM BIOS will initially load the palette registers such that the secondary green bit (bit 4) will be set for all the high order registers which require Intensity set for the four wire IRGB 16 color displays. This scheme allows the color selection to resemble a CGA's color selection. Any of the color fields which contain four bits (i.e. attribute bytes and color planes) actually select their respective palette register for the selection of color signals are to be output.

Mode Control Register (10h)

The Mode Control Register is a write only register which resides at index 10h in the attribute controller at I/O address 3C0. This register specifies the major operational mode and some other characteristics of selected modes. The Mode Control Register format is as follows:

In Alphanumeric mode bit 3 ties up with the MS bit of the text attribute byte to enable MS attribute bit to either be the Blink Enable bit when bit 3 is set or to enable the MS attribute bit to be that Background Intensity bit when bit 3 is reset. The blink rate is 16 display frames ON and 16 display frames OFF which is half the cursor blink rate. In Color Graphics Mode, setting bit 3 allows for a specific pixel to alternate between two colors by toggling COL3 at the blink rate.

Bit 2 when set enables the special line graphics characters originally designed for the MDA by causing the ninth dot to be the same as the eight dot for an effective 9x14 character cell.

Bit 1 when set selects the monochrome display attributes and when clear selects color display attributes.

Bit 0 selects graphics mode when set and Alphanumeric mode when reset.

Extended Graphics Border Register (11h)

The Extended Graphics Border Register is located at index 11h in the attribute controller registers at I/O address 3C0. It is also called the Overscan register and is a 6-bit wide write only register. Its function is to specify the Extended graphics mode border color. It can be locked out by setting bit 5 in the IGA Extended Mode Control Register (See page 29).

The format of the Extended Graphics Border register is the same as the Palette Registers (see page 36). When in monochrome mode the Extended Graphics Border register should be set to zero.

Color Plane Enable Register (12h)

The Color Plane Enable Register is a write only register residing at index 12h in the attribute controller at I/O address 3C0. Its function is to enable or disable which color planes are active for producing video, thus acting as an overall palette selector. The format is as follows:

When bits 0-3 are set to '1's, the corresponding color plane is enabled.

The two bits 4 and 5 allow for diagnostics to be run on the hardware by selecting which two color plane's outputs will be gated to bits 4 and 5 of the Status Port Register at 3BA / 3DA. The Following table gives the correspondence between the video status MUX bits and the Status Port.

The upper case letters represent the primary colors and the lower case letters represent the secondary colors. The 1, 1 case is not used.

Horizontal Panning Register (13h)

The Horizontal Panning Register is a write only register residing at index 13h in the attribute controller at I/O address 3C0. Its function is to select the number of pixels to shift the video date horizontally left. Panning is available in both alphanumeric and graphics modes. The monochrome alphanumeric shift factor is a maximum of 9 pixels. The maximum shift factor for all other modes is 8 pixels. The bit layout of the Horizontal Panning Register is as follows:

For the 9-bit maximum monochrome alphanumeric mode the shift sequence is pixel 8, then pixels 0 through 7. For all other modes the pixel shift sequence is pixels 0 through 7.

Sequencer Registers

The Sequencer is a hardware grouping within the Extended graphics controller which controls video memory accessing, character clocking and character generator mapping. The Sequencer registers consist of an address register with four control registers which are indexed by the address register. Index position zero though listed to select the Reset register is not required in the PC1640 IGA and is not implemented. The remaining registers corresponding to index values 1 through 4 respectively are the Clocking Mode register, the Plane Mask register, the Character Set Select Register, and the Memory Mode register.

Sequencer Address Register

The Sequencer Address Register is a write only register at I/O address 3C4 which selects which sequencer register is configured to I/O address 3C5. The bit layout of the Sequencer address register is as follows:

Clock Mode Register (3C5, 1)

The Clock Mode Register is a write only register which resides at I/O address 3C5 when the index register contains 1. Its format is as follows:

Bit 3 controls whether the dot clock will be a direct function of the master clock rate or divided by two. Setting bit 3 causes the input clock to be divided by two. This is used for 320 pixel wide graphics.

Bit 2 when cleared causes the serial video shift registers to be loaded every character clock. Setting bit 2 causes the load rate to be every second character clock. Bit 2 should be cleared when two of the shift registers are chained together for 16-bit character columns.

Bit 0 controls the number of dot clocks generated by character row. It should be cleared for monochrome mode (9-bit wide characters) and set for color mode characters (8-bits wide).

Color Plane Select Register (3C5, 2)

The Color Plane Select Register is a write only register which resides at I/O address 3C5 when the index register contains 2. Its format is as follows:

Setting Bits 0 - 3 write enables the respective memory plane. The CPU can write to any combination of display memory planes in one write cycle by setting the respctive bits. Bits 0 &1 and bits 2 & 3 should have the same values when odd/even modes are selected. (See page page 42 for Odd/Even mode details.)

Character Set Select Register (3C5, 3)

The Color Plane Select Register is a write only register which resides at I/O address 3C5 when the index register contains 3. Its format is as follows:

There are four alternate character sets per character map each containing 128 characters each thus allowing up to 512 characters to be accessible for any given screen. In addition the IGA Extended Mode register (bit 3) enables an alternate set of character maps to be selected for an extended total of 1024 available characters. The alternate map character selections is disabled then character map select A equals character map select B (that is, bits 0 & 1 equal bits 2 & 3. When enabled, attribute bit 3 selects when reset selects character map A and when set selects character map B. The following table gives the character set selections for the combinations of bits 0 - 3.

The dashes mean disabled and that attribute bit 3 becomes the intensity select bit.

When the IGA Extended Mode Register bit 3 is set then an alternate set of character maps are enabled from plane 3 and in this case the map numbers in the table should be logically incremented by 4. The following figure illustrates the complete PC1640 character set organization.

Memory Mode Select Register (3C5, 4)

The Memory Mode Select Register is a write only register which resides at I/O address 3C5 when the index register contains 4. Its format is as follows:

Bit 1 indicates that 256Kb of display RAM is present and should always be set on the PC1640.

Bit 2 when set selects chained addressing mode whereby even CPU address access character sets 0 and 2 while odd CPU addresses access character sets 1 and 3. When bit 1 is cleared, unchained addressing mode is selected and CPU accesses sequentially access data within the character bit maps.

Graphics Controller Registers

The Graphics Controller is a hardware grouping within the Extended graphics Controller which directs memory data to the attribute controller and to the CPU. In graphics modes serialised memory data is sent to the attribute controller. The Graphics Controller and the Attribute Controller are the two logic groupings which make up a total functional logic grouping called the Video Controller. The Graphics Controller registers consists of an address register and nine write only data registers.

Graphics Controller Address (3CE)

The Graphics Controller Address Register is a write only register at I/O address 3CE which serves as an address pointer for nine data registers at I/O address 3CF. The bit layout is as follows:

Bits 0 - 3 select the active register at I/O address 3DF.

Set/Reset (3CF, 0)

The Set/Reset Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 0. Its format is as follows:

The value in Bits 0 - 3 is written to plane 0 - 3 respectively, providing that the corresponding bit in the Enable Set/Reset register (below) is also set and that Graphics Mode Register 1 is programmed for write mode 0 and that the CPU data bit being written contains a 1.

For example if it were desired to write bits 7, 5 and 0 of a particular display location with light cyan then the Set/Reset register bits 3-0 would be set to 1011 binary (the pattern for light cyan), then the Enable Set/Reset register (page 44) is set to 0Fh and the particular display memory location would be written with 1010001 binary. The bit positions containing zeroes would remain unchanged and the pixels corresponding to bits 7, 5, and 0 would be light cyan. The equation for bit number to pixel number translation is: Pixel Number = (7 - Bit Number).

Enable Set/Reset (3CF, 1)

The Enable Set/Reset Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 1. Its format is as follows:

Setting Bits 0 - 3 will qualify the corresponding Set/Reset register bit to be written as described above. If write mode is 0 and Set/Reset is not enabled on a color plane, the plane's original contents are preserved.

Color Plane Compare Register (3CF, 2)

The Color Plane Compare Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 2. The Color Plane Compare register is activated when the Graphics Mode Register 1 (page 47) bit 3 is set enabling compare mode. When color compare mode is active, CPU reads of the display RAM area will return the results of a comparison between the Color Plane Compare Register and the color planes rather than the actual memory contents.

The Color Plane Compare Register is as follows:

The color pattern in bits 0 - 3 is compared with the memory location being read by the CPU. The bits returned represent which bits actually match the color pattern. The Color No Care register (described below) specify which planes participate in the comparison.

In the example for writing light cyan using the Set/Reset register, loading the color compare register with 1011 binary and reading the same display memory location would return the 1010001 binary value written. This is interpreted to mean that the pixels corresponding to bits 7, 5 and 0 are light cyan and the other pixels are some other color(s). To determine what other colors are in the same byte would require either performing a color compare scan of the 15 other color combinations or discreetly reading each of the color planes and considering what color the four bits for each pixel actually represent.

Data Rotate Register (3CF, 3)

The Data Rotate Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 3. This register controls a number of logical operations which can be performed when the CPU writes to the display RAM. Its layout is as follows:

The Function select field (bits 3 & 4) select one of four functions which can be performed between the existing contents of a memory plane and the new data being written. These operations are as follows:

When bits 3 and 4 are both reset, data from the CPU replaces the existing data and no logical operation is performed.

When a logical operation is enabled, the planes which are write enabled (see Color Plane Enable register) will be read and the specified logical operation performed between the existing contents and the data from the CPU and the resultant value stored in the respective display memory plane.

Bits 0 - 3 control a Rotate Right function on CPU data being written to the display planes. When write mode zero is programmed in the Graphics Mode register 1 (See Below), the contents of bits 0 - 3 represent the shift count which will be performed on the data from the CPU. The rotate is end around, the LS bits are rotated to the MS bits and the resultant value is written to the selected memory plane(s).

Color Plane Read (3CF, 4)

The Color Plane Read Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 4. Its format is as follows:

The CPU reads from whichever of the four color planes in display RAM selected according to the Read Select field. If the original contents of the color paletter registers are maintained then the selection relates to the IRGB color signals as follows:

Bit 2 is also connected with the read select decoding and should be maintained reset else no plane will be selected for reading.

Graphics Mode Register 1 (3CF, 5)

The Graphics Mode Register 1 is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 5. Its format is as follows:

Bit 5 controls the configuration of the four serializer shift registers within the graphics controller. In the normal case when bit 5 is reset, data from planes 0 - 3 are shifted out of shift registers 0 - 3 respectively going out MS bit first. When bit 5 is set to one then the even numbered bits are shifted out of the even numbered shift registers and the odd numbered bits are shifted out of the odd shift registers. This means that shift register 0 shifts bits 6, 4, 2 & 0 of Plane 0, followed by bits 6, 4, 2 & 0 of plane 1. Shift register 1 shifts bits 7, 5, 3 & 1 of Plane 0 followed by bits 7, 5, 3 & 1 of Plane 1. Shift registers 2 and 3 perform the same even/odd shifting pattern for color planes 2 & 3 as described above.

Bit 3 when clear enables the Color Plane Read register to control the color plane selection of CPU reads. When bit 3 is set then the Color Plane Compare register controls the CPU data read back (as described on page 44).

Bits 0 and 1 form a two bit Write Mode field which specifies the manner in which the IGA handles graphics data written to the memory planes. The following table gives the valid options:

The 1,1 state is not legal and should not be used.

Graphics Mode Register 2 (3CF, 6)

The Graphics Mode Register 2 is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 6. Its format is as follows:

Bits 2 and 3 form a two bit field which specifies the regeneration buffer origin and size parameters as follows:

Setting bit 1 causes the processor address bit A0 control the selection of odd/even memory planes rather than contiguous odd/even addresses. The usual function performed by address bit A0 is shifted to the high order address bit.

Color No Care Register (3CF, 7)

The Color No Care Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 7. Its format is as follows:

This register ties up with the Color Compare register and can be considered a color compare mask in that setting bits in the 'No Care' register inhibits the corresponding color plane from participating in the comparison process when a color compare read is performed.

Write Mask Register (3CF, 7)

The Write Mask Register is a write only register which resides at I/O address 3CF when the Graphics Controller Address Register contains 8. Its format is as follows:

Resetting bits in the Write Mask register disables the respective bits from being written to in the display planes. The Write Mask register is programmed to all ones during display mode initialization so that the all eight bits are normally stored into display memory.

The Write Mask register affects all data written by the CPU including the rotate and logical operations. The hardware performs a read-before-write operation in order to preserve the protected bits.

EGA Mode CRT Controller Registers

The CRT Controller is a hardware grouping within the IGA which controls horizontal and vertical synchronization as well as cursor, underline and blink timing. It also generates addressing for the display regeration buffer and dynamic RAM refresh controls.

The CRT Controller contains data 27 registers which are accessed through an index register which must be loaded prior to accessing a particular CRTC data register. The CRTC data registers reside at either I/O address 3B5 or I/O address 3D5 depending on whether the IGA is operating in monochrome mode or color mode respectively.

This alternate I/O addressing scheme is so that an alternate adapter such as a MDA or a CGA can be fitted in the expansion slots and there will be no I/O address conflicts with the other display adapter's CRTC. This means that the system can only support one color adapter and one monochrome adapter at the same time. If the IGA is driving a monochrome monitor then a CGA can be fitted in the expansion slots. Conversely, if the IGA is driving a color display then only a monochrome adapter can be fitted in the expansion slots. In no case can an EGA be fitted in the expansion slots when the IGA is active because the other EGA will overlay the IGA's ROM BIOS as well as the registers in the 3CX I/O address range. It is also possible to configure the IGA to overlay other display adapter's display RAM.

An additional register, the Status PORT Register, is not technically part of the CRTC but is closely associated with it also explained with this hardware grouping.

CRT Controller Address Register

The CRT Controller Address Register is a write only register which resides at either I/O address 3B4 or I/O address 3D4. When written to, its contents represent an index into the CRTC data registers at I/O addres 3X5 (X=B for Monochrome and X=D for color).

Values greater than 18h are not valid and should not be used.

Horizontal Total Register (3B5/3D5, 0)

The Horizontal Total Register is a write only register which resides at I/O address 3X5 when the CRT Controller Address Register contains 00h. Its format is as follows:

The Horizontal Total Register specifies the number of characters (minus 2) in the horizontal scan interval inclusive of the retrace period. This value is the basis of all horizontal (and vertical) timing.

Horizontal Display End Register (3B5/3D5, 0)

The Horizontal Display End Register is a write only register which resides at I/O address 3X5 when the CRT Controller Address Register contains 01h. Its format is as follows:

The Horizontal Display End value is the number of characters to be displayed per horizontal line. The actual number of characters displayed per horizontal line is one less than the contents of this register.

Start Horizontal Blanking Register (3B5/3D5, 2)

The Start Horizontal Blanking Register is a write only register which resides at I/O address 3X5 when the CRT Controller Address Register contains 02h. It is formatted as follows:

The Horizontal blanking signal becomes active when the horizontal character count is equal to the value in this register.

End Horizontal Blanking Register (3B5/3D5, 3)

The End Horizontal Blanking Register is a write only register which resides at I/O address 3X5 when the CRT Controller Address Register contains 03h. It is formatted as follows:

The Horizontal blanking signal becomes inactive when the lower 5 bits of the horizontal character count is equal to the value stored in bits 0 - 4 of this register.

Because of the sequential access to display memory by the CRTC, the video data is skewed relative to the horizontal timing. The Display Enable Skew value corrects for this skew by causing a delay of a number of character clocks equal to the value stored in bits 5 and 6.

The following equation specifies the value for bits 0 - 4: End Horizontal Blanking = (Start Blanking Value + Width of Blanking) Modulo 32.

Start Horizontal Retrace Register (3B5/3D5, 4)

The Start Horizontal Retrace Register is a write only register which resides at I/O address 3X5 when the CRT Controller Address Register contains 04h. Its format is as follows:

The Horizontal retrace signal becomes active when the horizontal character count is equal to the value in this register.

End Horizontal Retrace Register (3B5/3D5, 5)

The End Horizontal Retrace Register is a write only register which resides at I/O address 3X5 when the CRT Controller Address Register contains 5. Its bit assi