.he Speech Interface .fo 2.11/#  Speech Interface 2.11  Contents Introduction Details Circuitry 6301/8086 Communications Address Allocation .pa Introduction This chapter describes the hardware used to implement the interface between the microphone and the voice driver circuitry. It is documented purely as interest value and for the sake of completeness. It does not provide any great detail on the the 6301 processor and it's interface to the 8086 processor since the likelihood of anybody implementing a different speech driver using the same interface is extremely remote due to its inherent complexity. .pa Details The Interface Board on the Portable contains an area of circuitry, which forms the interface between the user (via a microphone) and the speech driver software. It is based upon a analogue-to-digital conversion stage, controlled by a 6301 processor. A block diagram of the speech interface system is illustrated on Figure 1. Figure 1. Speech Interface .pa The prime purpose of the interface is to convert the analogue speech input from the microphone into digital format for use by the speech driver software. Circuitry This consists of a multi-stage signal processing circuit. The first stage is a lowpass filter stage which acts as a pre-emphasis network, which increases the high frequency components of the audio frequency signal relative to the lower frequencies. (It is actually a passive lowpass filter with a cut-off frequency of 1600 Hz). The second stage is a two-stage amplifier section, which also band limits the signal to within a frequency spectrum 340 Hz to 4 KHz. The gain of the amplifier section is controlled by the 6301 processor. It does this by switching in different resistor values into the feedback network on the amplifiers. This allows various gain settings from 0 to 65 dB to be set in discrete steps. The third stage in the circuit is the actual a-d converter which is based upon a sample and hold arrangement. The sample rate is controlled by a clock signal supplied from the on board Timer circuit. The same clock output from the timer can also be used for setting up the RS232C port for an internal split speed baud rate clock, but will affect the operation of the speech interface circuit. The value programmed into the timer is set by the speech driver software. An offset voltage is also supplied from the 6301 via a d-a converter for biasing the audio signal to set it into the required sample range. The digitised audio samples are read by the 6301 and transferred to the 8086 processing environment using an elaborate communication mechanism. This involves a data transceiver and the use of interrupts. 6301/8086 Communications When the 6301 has data to transfer to the 8086, it generates an interrupt which is supplied to the interrupt controller (PIC) on the CPU and Display Board (via interrupt request line - IR2). The associated interrupt service routine clears the interrupt by writing to an I/O control port (12H). This is detected by the 6301 (by monitoring one of it's input ports) and acts as a "request for data" signal. The 6301 sends a byte data to the transceiver which forms the interface between the 6301 and the 8086 data bus, and also sets a flag (LP23 - wired to bit 4 of the parallel port which is primarily used by the printer interface - I/O port 24H). The 8086 polls the parallel port line D4 and reads the data from the transceiver (I/O control port 10H) on detecting an active signal on LP23. The final operation of the data byte transfer sequence is performed by the 8086. This is clearing LP23 by writing to another I/O control port (16H). This action also indicates to the 6301 that another byte of data can be transferred as necessary. The number of data bytes to be transferred is signified by the first bytes sent from the 6301. When the 8086 wishes to send data to the 6301, it does so by generating a 6301 interrupt. This is achieved by simply writing to the I/O control port 14H and then after a delay writing to port 12H. The action of writing to 14H, produces an active low state on the 6301 Interrupt Request line IRQ1, via a D-type latch. The 6301 interrupt service routine clears the interrupt and also sets the flag LP23 (wired to bit 4 of the parallel port as described above) to indicate it is ready to receive data. The 8086 polls the parallel port line D4 and sends the data to the transceiver (I/O port 10H) on detecting an active signal on LP23. The 8086 then clears LP23 by writing to I/O control port 16H. This signifies to the 6301 that data is available and enables it to read the data stored in the transceiver. This process continues with the 6301 signalling it is ready to receive data using the LP23 handshake mechanism depending on the number of bytes to be transferred. This is specified by the first bytes of data sent to the 6301. .pa Address Allocation The following addresses located in the system I/O space are used for communicating with the 6301. Address Function Access 10H 8-bit Data Port Read/Write 12H Interrupt Clear Write only 14H Generate 6301 Interrupt Write only 16H Clear LP23 Write only 36H Generate 6301 NMI Write only 24H LP23 status (bit 4) Read only Ports 12H, 14H and 16H do not require data to be sent to generate the respective function. The 6301 NMI is generated by writing FFH to the bit wide port 36H (only bit 0 is significant).