The ICL Quattro
Normally, describing a vintage computer, I like to start with a picture of it. This time, I can't; for reasons of space, I had to scrap the case, power supply, and drives, leaving me with a few cables and this:
If you want to see what one looks like fully assembled, I direct you to old-computers.com. Mine differed a little from the one shown; it had a full-height floppy drive, the 'custom synchronous port' was replaced by a SCSI port, and the hard drive was connected to the SCSI controller by means of an MFM-to-SASI bridgeboard. It also had two sets of serial ports rather than just one, but we'll come to that.
The power connector on the backplane has six pins, but on mine only four were connected: Ground, +5v, +12v and -12v. Ground, +5v and +12v are carried on PCB layers, while the -12v line is the lower of the thick traces visible in the picture. Possibly the other thick trace (corresponding to the pin marked in white) was -5v on other ICL PCs?
All the power lines except the one I've marked in green feed to pairs of pins on the eight slots. The green one feeds only to a single pin.
The CPU board
Components on the CPU board include:
- Two 8k ROMs, holding odd and even bytes for the boot ROM. This isn't a full IBM-style BIOS; it can perform a self-test, boot from hard or floppy drives, and perform a memory dump to floppy or to a tape streamer.
- The CPU (under the heatsink in the centre), an 80286.
- An i8237 DMA controller
- A 146818 real-time clock, and a battery for it.
- An 8259 interrupt controller.
In addition to the bus connector, there are two smaller ones: the one on the left connects to the reset button, and the one on the right to the power-on LED.
The I/O Boards
The I/O boards each have:
- A Z80-SCC
- Two 8259 PICs
- Six SCN2661 USARTs
The 50-pin connector on the end connects (by means of a short ribbon cable) to the backplate with the sockets. A normal Quattro would have one of these boards and mounted the backplate on its back panel, but this one had two boards. The opening in the case was filled by a blanking plate, through which two metre-long cables emerged. These were extensions of the 50-way ribbon cables, and ran from the cards to a separate box containing both the backplates.
The two boards are given different base addresses (0xFE50 versus 0xFF50) by means of jumpers — perhaps the two links LK8 and LK9, which are present on one board but not the other.
The memory boards
Not a lot to say here. Each board has 32 M5M4256 memory chips, giving 1Mb storage. The red jumpers in the bottom right-hand corner of the board presumably select its base address.
The floppy / SCSI board
The two big chips on this board are an NCR 5380 SCSI controller, and an MB8877A floppy controller (compatible with the WD1793).
I/O port mapping
I/O ports accessed by the boot ROM include:
- Memory paging. Each of these ports takes a 16-bit value, and maps to a
16k range of CPU address space:
Port Range 0000 00000-03FFF 0002 04000-07FFF 0004 08000-0BFFF ... 007E FC000-FFFFF
The value written is a 16-bit word, indicating which 16k bank of physical memory gets mapped in at that position. In theory this scheme would support 64k banks of 16k each for a total of 1G physical memory, but in practice the limit is probably much less. The BIOS seems to assume that only bits 0-9 of these registers apply to memory banking, which would give a maximum of 16Mb.
- Memory paging for the four DMA channels. Using the same scheme as for CPU
memory paging, this controls which 64k range will appear when memory is
accessed by the DMA controller.
Port Range 0080 DMA0, 0000-3FFF 0082 DMA0, 4000-7FFF 0084 DMA0, 8000-BFFF ... 009E DMA3, C000-FFFF
The BIOS assumes that operating systems will only touch the first two of each set of four registers (ie, that all transfers will take place in the first 32k of these address windows). The third and fourth registers in each set are used as a 'warm boot' flag; if each channel has its third register set to 0ADh and its fourth register set to 0ECh, this is a warm boot and the memory test is skipped.
- 00D2, 00D4
- Main interrupt controller. Interrupt masks are written to port 0D2h.
- The DMA controller. The floppy controller uses channel 0, the SCSI controller uses channel 2.
- 146818 real-time clock and battery-backed RAM:
0100-D: Date and time, and 146818 registers 010E: Last self-test failure 0: Memory 1: Serial ports 2: Clock 3: Hard drive controller 4: Hard drive(s) 5: Floppy drive 6: Floppy drive DMA 7: 80287 8: Misc 9: Mapping RAM A: Battery-backed memory B: Interrupt system C: Firmware/PROM system 0FFh at cold boot. 010F: Set to 3 if a self-test fails, 1 or 2 if in a self-test. 0111-2: Memory size, kilobytes 0113-4: Clock ticks per second, divided by 64. 0115-8: DWORD address of configuration block (loaded from boot floppy). 0119: If bits 0-3 nonzero, skip RAM test. If bit 4 set, boot from floppy 011A: Internal hard drive (SCSI 0) type, 0 for none 011B: External hard drive (SCSI 1) type, 0 for none 011C: External hard drive (SCSI 2) type, 0 for none
- The IRQ handler for IRQ2 associates these with the PIC at FE6C. May well be a typo for FE50-FE67.
- FE50-FE53, FE54-FE57, FE58-FE5B, FE5C-FE5F, FE60-FE63, FE64-FE67
- The six USARTs on the secondary serial card, if present (cf the description of the primary serial card below).
- The Z80-SCC on the secondary serial card (see below).
- FE6C-FE6D, FE6E-FE6F
- The two PICs on the secondary serial card (again, see below).
- NCR 5380 SCSI controller
- MB8877 floppy controller
- Bit 0 is floppy head select.
- Selects floppy drive. 0 or 1, or 0FFh for neither.
- FF50-FF53, FF54-FF57, FF58-FF5B, FF5C-FF5F, FF60-FF63, FF64-FF67
- The six 2661 USARTs on the primary serial card. The BIOS uses three of these; USART 0 (at FF50) is the system console, to which boot messages are sent. USARTs 1 and 3 (at FF54 and FF5C) are used for auxiliary I/O; USART 1 for functions 3-6, and USART 3 for functions 7-10.
- Z80-SCC channel B command register.
- Z80-SCC channel A command register. The BIOS writes 00 09 C0 to this port during initialisation (the latter two bytes are 'force hardware reset')
- Input PIC on the primary serial card (handles the USARTs' "character received" interrupt).
- Second PIC on the primary serial card (handles the USARTs' "ready to transmit character" interrupt).
- Value written at initialisation: 2.
CCP/M appears to associate interrupts as follows:
- The floppy controller.
- Serial ports: Character received. If a serial port interrupts, the handler interrogates the PICs at FF6Ch and FE6Ch to find out which port interrupted, and reads a character from it.
- Timer interrupt (from the 146818 RTC).
- Associated with the Z80-SCC at FF68h-FF6Bh
- Serial ports: Ready to transmit. The handler interrogates the PICs at FF6Eh and FE6Eh to find out which port interrupted, and sends it a character if one is buffered.
- The SCSI controller.
The boot ROM provides the following BIOS functions. They can be accessed by a far call to FFFF:FFF5 with PSW on the stack (the function returns with IRET). It doesn't preserve registers, unlike the IBM PC BIOS.
AL=0: Console input status. Returns AL=0FFh if character ready, else 0. AL=1: Console input. Wait for character, return it in AL. AL=2: Console output. Write character in CL. AL=3: Auxiliary input status (USART 2) AL=4: Auxiliary output status (USART 2) AL=5: Auxiliary input status (USART 2) AL=6: Auxiliary input status (USART 2) AL=7: Auxiliary input status (USART 4) AL=8: Auxiliary output status (USART 4) AL=9: Auxiliary input status (USART 4) AL=10: Auxiliary input status (USART 4)The jump table used by this function is longer than this, but the extra functions don't appear to be usable through this interface. Many take parameters in BX, which is corrupted by the entry handler above.
The BIOS ROMs also both contain the string 'Andy Champ'.
John Elliott 1 August 2010.