2.0 Firmware

This section describes the Amstrad PPC Resident Operating System (ROS). It defines the interfaces to all the interrupt service routines provided by the Amstrad PPC ROS firmware (ROM) and all RAM locations used by the ROS.

The following copyright message is stored at the beginning of the ROS starting at location 0003 (relative to its origin at FC000):

(C) Copyright 1987 AMSTRAD plc

The ROS physically occupies the highest 16K bytes (in the address range FC000 to FFFFF) in the 1 Mega Byte addressing range of the 8086-2 CPU (See Figure 1.1). The total 64K byte address range from hexadecimal F0000 to FFFFF is reserved for system ROM and this contains the reset and initialization address FFFF0. The PPC address decoding for the system ROM area is such that the ROS ROM which actually resides at FC000 is repeated four times in the address space starting at F0000.

Note that all address constants in this document are in hexadecimal form unless otherwise noted.

All calls to the ROS firmware should be made through the software interrupts disclosed in this manual. Application programs should not attempt to access the locations within the ROM area directly. Amstrad reserves the right to modify the coding within the Resident Operating System ROM as it sees fit.

The firmware provides a set of resident software routines which perform various services and I/O functions:

1. Power-Up initialization and Self Test.
2. Keyboard input.
3. Video display of characters and pixels.
4. Video buffer screen dumping.
5. Character I/O to the printer and serial ports.
6. System clock and real time clock support.
7. Floppy Disk I/O including format, read and write.

To ensure hardware independence of application programs all I/O processes should be done using the ROS. This avoids possible problems due to any hardware modifications and/or enhancements.

2.1 Power-Up initialization and Self Test

The Power-Up initialization and Self Test function is entered at location FFFF0, the CPU reset entry point. This is a collection of routines which perform all necessary hardware initialization and self tests, setting up of the BIOS RAM variable area, initialization all the interrupt locations used by the ROS, initialization of expansion slot peripheral ROMs and the running of floppy diskette or hard disk bootstrap.

The ROS does not use the System RAM (User RAM Area) for stack or program variables until it has been successfully tested. If a RAM error is found an error message should be displayed correctly, assuming there is no other fault that may result in incorrect operation of the CPU or Video Circuitry.

The Power-Up initialization and Self Test process proceeds as follows:

1. Disable maskable and non-maskable interrupts.
2. Run self test which include the following:
   • Checksum of the ROS.
   • Test all system RAM.
   • 8237 DMA controller.
   • 8253 Programmable Interval Timer.
   • 8255 Programmable Peripheral Interface.
   • RTC counting.
   • The system serial interface.
   • The system printer interface.
   • 8259 programmable interrupt controller.

   After a system reset all the self tests except the RAM tests are rerun. If the three option links in the least significant part of the system printer status register are set to all ones then diagnostic mode is selected and if the diagnostic test ROM pack is found, it is entered, otherwise only the keyboard and disk tests are run before external ROM initialization and system startup is attempted.

   Refer to section 2.2 for the individual power-up self test details.

3. Check the RTC.

If the RTC registers are incorrect then it they are loaded with default values.

4. Initialise the 8253 Programmable Interval Timer.

Set up counter 0 to interrupt every 54.9337 milliseconds. Set up counter 1 to generate an output signal with a period of 15.13 microseconds. Disable counter 2.

5. Initialise the 8237 DMA controller.

Set up DMA channel 0 for memory refresh. Disable channel 1, 2 and 3.

6. Initialise the 8259 Programmable Interrupt Controller.

Disable (mask) all interrupt levels. Note that levels 0, 1 and 6 are enabled (unmasked) later.

7. Initialise the Write Status Registers.

Write Status-1 is initialised with the number of drives fitted and the default Video Mode. This information is determined by checking if a second floppy drive is fitted to the FDC and by reading PPC switches 4 and 5. The ROS also sets or resets bit 1 in the status register depending on whether or not an 8087 NDP is installed. See section 1.8 for further System Status-1 information.

Write Status-2 is initialised according to the amount of memory installed. The ROS assumes a minimum of 512K bytes and that additional RAM may be added in contiguous 32k byte increments up to the maximum of 640K bytes. The additional memory is sized according to the following procedure. The segment address of each of the four 32K byte RAM blocks is written to the first two bytes of each respective block. The segments are then verified from low to high until a non matching segment address or the last block is encountered. The setting of the Write Status-2 register is according to the RAM0-RAM4 table in section 1.8.3.

8. Initialise the ROS variable area in system RAM.

The ROS uses variables in the address range of 00300 to 00500. Refer to section 2.4 (RAM Variables) for a complete description of these variables and their respective initialised values.

9. Initialise the first 32 Interrupt Vectors.

The first 32 interrupt vectors are set up to reference the ROS routines as listed below. Software interrupt routines which do not perform any function reference a dummy routine that simply does a return from interrupt (IRET) instruction. Hardware service interrupts which do not perform any function reference a dummy (HWIRET) routine which issues a nonspecific end-of-interrupt to the 8259 interrupt controller and then executes an IRET instruction.

The interfaces to the above routines are detailed in section 2.3.

The 8259 PIC is programmed such that its IRQ0 - IRQ7 interrupt levels use CPU interrupt vectors 8 - 15 as indicated in the above table.

10. Initialise and Test the Disk interface.

The initialise function of interrupt 19 in invoked followed by the disk test (see 2.2.12).

11. Keyboard Self Test.

The Keyboard microcontroller returns 0AAh upon successful completion of its power-up self test (See 2.2.13).

12. Initialise the 8259 Interrupt controller.

Enable 8259 interrupt controller on levels 0 (8253 counter 0), 1 (keyboard scan code receiver) and 6 (765 floppy disk controller). All other 8259 interrupt levels are masked.

13. Display the ROS sign-on message.

During power-up the ROS checks the RTC. After the sign-on message has been displayed, the ROS checks if the date is reasonable, that is, other than 1980. If so then the last startup and current date are considered valid and the time and date of last switch-on are displayed. If a date of 1980 is detected it is assumed that time and date are invalid and warning messages to "Please Set Time and Date" and "Fit new batteries" are output.

14. Enable the NMI.

If a NMI occurs the default ROS interrupt handler displays a RAM parity error message and hangs the system. This condition can only be rectified by switching the machine off.

15. Initialise all external ROMs.

The ROS checks for external ROMs between addresses C0000 and F4000 in 800h (2k) byte increments. An external ROM which conforms to the following specification will be initialised by the ROS:

1. The first two bytes contain the hexadecimal value 55AA.
2. The next two bytes contain the size in 512 (1/2K) byte increments.
3. The next byte is the initialization routine entry point.
4. The LS byte of the byte sum of the ROM is zero.

When a ROM conforming to this specification is located then the initialization entry is called.

If the checksum test fails then an error message is displayed and initialization is not called.

17. System Clock initialization.

After all tests have been run the ROS sets up the 32-bit system clock location in RAM (at 046Ch) by reading the RTC time and converts this to the number of system clock interrupts since midnight. (See section 2.3.3).

18. Diskette Bootstrap.

The ROS attempts to load the bootstrap sector (from drive A, side 0, track 0, sector 1) into memory at 07C00h. If the bootstrap sector loads successfully it is given control (far jump to segment 0000 offset 7C00). If after 10 retrys the bootstrap sector cannot be loaded then the ROS displays a message prompting the user to insert a system disk into drive A and press a key. The ROS then waits for the key press and repeats the bootstrap procedure.

2.2 Power-Up Self Tests

On Power-Up or following a system reset, the ROS performs a series of self tests on the hardware to verify proper operation. When a test failure occurs, the ROS displays an error message on the primary display device and the system is locked up. The keyboard interface is treated differently in that the ROS repeats keyboard self test until it is successful.

The ROS executes all self tests except when the option links (LK1 - LK3) are all set (See section 1.10.3), the ROS will only run the keyboard interface test and the disk test. If either of these two tests fail an error message is displayed but the error is ignored. This allows the system to be brought up for diagnostic testing.

When a soft reset (Control, Alt and Del) is issued the ROS performs all the self tests except the system RAM (User Area RAM) test and the video RAM test. The program calling the ROS initialization after a soft reset must store the value 1234h in system location 0:478h and this value notifies the ROS firmware that a soft reset was requested. When the 1234h value is recognized a full hardware reset is performed and this will reset all external peripheral cards in the expansion bus. A special entry flag value, 1235h performs the ROS Power-Up testing as described above but inhibits the full hardware reset from occurring. The ROS sets the contents of the word location at 0:488 to 1234h when it completes its testing.

2.2.1 Test Procedure.

Upon entry the ROS performs the necessary functions to start video output by the IDA to the LCD (regardless of the configuration switches), and then stores the message ("Please wait") on the first line of the screen to indicate that self testing is in progress and as each successive self test is started a dot is displayed on the screen.

The tests are run in the following order:

1. ROS checksum test.
2. Direct Memory Access (8237) Controller test.
3. Programmable Interval timer (8253) test.
4. Programmable Peripheral Interface (8255) test.
5. Real Time Clock (HD146818) test.
6. Asynchronous Communications Element (8250) test.
7. Parallel Printer Port test.
8. System RAM test.
9. Programmable Interrupt Controller (8259) test.
10. Disk test.
11. Keyboard Interface test.

The ROS uses the stack during the Disk test, the Keyboard interface test and the Programmable Interrupt Controller test. All other self tests are executed without using either the stack or any RAM variables.

2.2.2 Test Methods.

Most of the device diagnostic tests consist of a Data Path test and a Waveform test as described below:

Data Path test.

The data path test checks the read/write path between the CPU and a particular device. A pattern is written to a device and then read back to verify the integrity of the data path. The patterns are as follows:

All zeros.
All ones.
Sliding single bit and complement across 8 bits.

Waveform test.

The waveform test detects address decoding errors in a hardware device. The waveform test consists of selecting a specific address in a device, writing a test pattern (usually 0FFFFh) and verifying that the same pattern can be read back. The waveform test is done in both ascending sequential order (upwards) and descending sequential order (downwards) in order to check that the address decoding logic works correctly.

2.2.3 ROS Checksum Test.

All bytes in the Resident Operating System ROM are summed and then checked that the least significant byte of the sum is zero. If the check fails then an error message indicating faulty ROM checksum is displayed.

2.2.4 Direct Memory Access Controller test.

The upwards/downwards waveform test is used to confirm that the registers in the DMA controller chip can be addressed. Any failure will cause the faulty DMA error message to be displayed.

2.2.5 Programmable Interval Timer test.

The fiest 8253 test is a read/write data path test to counter 2 followed by a check that counter 1 counts at the correct rate. If either test fails an interval timer error message is displayed.

2.2.6 Programmable Peripheral Interface test.

The 8255 PPI tests consists of a data path test on each of the two system status channels (Status-1 and Status-2). The 8253 PIT OUT2 (Status-2) bit is also checked for proper operation. If either test fails the faulty real time clock error message is displayed.

2.2.7 Real Time Clock test.

The RTC seconds counter is tested to be counting at the correct rate. Next a data path test on the checksum byte of the NVR is run (and the checksum byte is restored). If either test fails the faulty real time clock error message is displayed.

2.2.8 Asyncronous Communications Element test.

This test confirms that the transmitter and receiver of the 8250 (i. e. the system serial port) are functioning correctly (at least in diagnostic mode).

The 8250 is configured in loop mode, 9600 baud, 8 data bits, 1 stop bit and no parity. Two test patterns are transmitted and the received patterns are checked. The status register is monitored for no parity, framing or overrun errors. If either received pattern does not equal the sent pattern or an error is set in the status register the faulty system serial port error message is displayed.

2.2.9 Printer Parallel Port test.

A data path test is performed on the printer data latch. If any incorrect test pattern is returned, the faulty printer port error message is displayed.

2.2.10 System RAM test.

The amount of System (User Area) RAM is determined using the procedure described in section 2.1 (This should always produce 640K as the answer ). The data path test is run on all available RAM followed by an upwards/downwards waveform test. If either test fails the faulty RAM error message is displayed.

2.2.11 Programmable Interrupt Controller test.

The 8259 tests consist of a data path test on the interrupt mask register and an interrupt acknowledge test to confirm that interrupts can occur and be serviced. If the test fails the faulty interrupt controller message is displayed.

2.2.12 Disk test.

The disk test attempts to establish whether the drives fitted to the system seek correctly. The test moves the read/write heads to track 10 on each drive. The ROS does not verify that the correct track was attained. If any errors are reported then a floppy disk controller error message is displayed.

2.2.13 Keyboard Interface test.

Upon power-up or reset, the keyboard self test is performed by the keyboard controller firmware. The keyboard returns keycode 0AAh to signify the successful completion of its testing. If any key code other than 0AAh is returned the keyboard error message is displayed amd keyboard reset is issued (which reruns the keyboard self test). The Keyboard test is repeated until the keyboard test passes. When test pass is received, the error message is removed from the screen and the test is exited as normal. During the keyboard test a short beep is sounded every five seconds to indicate that the test is in progress.

2.3 ROS Interrupts.

The first 32 interrupt vectors are initialised by Power-Up initialization. The software IRET and hardware HWIRET entries are dummy routines which require no entry or exit conditions and are not detailed here.

Any application program which replaces a default interrupt vector with its own entry point must not invoke any ROS interrupts from within its own interrupt service routine.

2.3.1 Interrupt 2: Parity Error (NMI).

The Interrupt 2 routine deals with system RAM parity error. The screen is switched to the default display mode, cleared and a RAM parity error message is displayed. The machine cannot be used until the power switch is cycled off and on again.

This routine does not use RAM for stack or program variables.

An application program which makes use of the 8087 NDP must supply an interrupt 2 service routine for the 8087 NDP.

CPU registers are used as follows:

Entry:

No conditions.

Exit:

Doesn't happen.

2.3.2 Interrupt 5: Print Screen.

The Interrupt 5 routine dumps the screen in character mode to the primary printer port. Since the screen dump is character based, attempting to dump graphic pictures to the printer may produce incorrect results. Characters that cannot be read back from the screen in graphics mode (using the video interrupt 16 read character function) are printed as spaces.

If a screen print is already in progress the interrupt takes no action.

The Print Screen Status variable (at address 00500) is set to 1 while the screen dump is in progress. When complete the variable is set to zero. If the screen dump is abandoned due to printer port timeout, the variable is set to 255.

CPU registers are used as follows:

Entry:

No conditions.

Exit:

All flags and registers preserved.

2.3.3 Interrupt 8: System Clock Interrupt.

The interrupt 8 routine is invoked by the system clock (counter 0 of the 8253). The default ROS routine does the following:

1. Increment the 32-bit system clock count held in RAM (location 0046C). If the clock reaches the 24 hour time (0001855000h) then the count is reset to zero and the 24 hour flag (location 00470) is set to 0FFh.
2. If the least significant byte of the system clock count is zero then the current time and date in the real time clock (RTC) is copied to the NVR. The time that is last copied from the RTC before the machine is switched off is displayed when the machine is next switched on.
3. If the disk motor timeout count is not zero then it is decremented by one. If the count reaches zero all the drive motors are turned off.
4. Invoke interrupt 28. Application programs that want to be interrupted by the system clock should use interrupt 28.

CPU registers are used as follows:

Entry:

No conditions.

Exit:

All flags and registers preserved.

2.3.4 Interrupt 9: Keyboard Interrupt.

The ROS Keyboard hardware interrupt reads a key code from the keyboard interface, translates the key code into a 16-bit key token using an internal translation table and the key token is put into the key token buffer. If the buffer is full the key token is discarded and a bleep is output on the speaker. The key tokenization for the most part consists of the high byte being the key number and the lower byte being the ASCII for the keycap. Those keys for which there is no ASCII equivalent the token consists of a unique high byte value with the low byte cleared. In the case of the new 101 / 102 key keyboard there are quite a few extra keys. There are extra [ALT] and [CTRL] keys as well as a dedicated cursor keypad. These keys basically return the exact same keycode as the originals except that preceding the keycode an extra one is sent to signify that the key pressed is one of the new keys.

Entry:

No conditions.

Exit:

All flags and registers preserved.

The ROS Keycode translation table is as follows (all values are hexadecimal) and the key names are the USA versions:

The following set of keys are the dedicated cursor keys. They produce different sequences of key codes depending on state of the [SHIFT] and [NUM LOCK] keys. In the base and [SHIFT + NUM LOCK] state the key sequence consists of the keycode expected from the corresponding key on the numeric keypad (with the [NUM LOCK] off) preceded by the extra key keycode (ie. E0h). With only [NUM LOCK] on the key sequence consists of the base sequence preceded by E0h,2Ah so there now are four keycodes in the sequence. The last variation is if the [SHIFT] key only is down. In this case the sequence as shown in the base case is preceded by E0h,AAh and again there are four keycodes in the sequence. All sequences of keycodes are treated in the same way by the ROS.

The last set of keys are classed as miscellaneous.

E0,37

CTRL or SHIFT Print Screen

E0,2A,E0,37

Print Screen

E0,AA,E0,35

Shift / on keypad

E1,1D,45

Pause

Key codes marked with '*' cause special actions as explained below.

The key code marked '+' is handled by ROS but cannot be produced by the US (101 key) version of the keyboard.

The table positions marked 'Ignored' are physically marked in the table by a value with the MS bit set and this causes the keyboard processor to ignore these keystroke combinations.

Note 1: The Numeric keypad keys will produce a different token depending on the state of the [Num Lock] and [Shift] keys. With [Num Lock] on and [Shift] down then Num Lock is cancelled and the Normal column tokens are produced. With [Num Lock] off and [Shift] down then the tokens in the Num Lock column are produced.

Note 2: Not all tokens listed in this table will be returned by the non-extended Get Key Token software interrupt (Int 22); some are discarded and some are modified when returned to the calling software. Refer to section 2.3.11 for complete details of the rules used when dealing with the extended keycodes produced by the extended keyboard.

2.3.4.1 Special Key Actions.

Some keys or set of keys invoke a special action as detailed below. Unless otherwise stated they do not result in any key tokens being inserted into the buffer.

1. [Ctrl]+[Alt]+[Del]: Reset.

When reset is detected, a system hardware reset is issued. The power-up initialisation process is entered but System RAM and video RAM tests are not run.

2. [Pause].

The ROS waits for another key to be pressed (except [PAUSE]), thus suspending any application that is running.

3. [Ctrl]+[Pause]: Break.

When break is detected, interrupt 27 is invoked and the keyboard buffer is cleared. Key token 0000h is then inserted into the buffer.

4. [PrtScrn]: Print Screen.

When print screeen is detected interrupt 5 is invoked, the ROS print screen function. If this entry point is maintained screen dump will continue to work. Some operating systems such as CP/M install a null pointer here. Typing [Ctrl+PrtScrn] invokes printer echo mode whereby all keystrokes are echoed to the printer. This mode can be toggled off by the same keystroke combination. Printer echo mode can also be toggled using [Ctrl+P].

5. [Ins]: Insert Toggle.

Each time the Ins key (keycode 52) is received, except in Num Lock mode, the Ins key toggle bit (bit 7 of RAM location 0:417) is inverted.

6. [Scroll Lock]: Scroll Toggle.

Each time the Scroll Lock key is pressed the scroll key toggle bit (bit 4 of RAM location 0:417) is inverted. Note that Ctrl - Scroll Lock (break) does not flip the scroll toggle.

7. [Caps Lock]: Caps Lock Toggle.

Each time the Caps Lock key is pressed the Caps Lock toggle bit (bit 6 of RAM location 0:417) is inverted.

8. [Num Lock]: Num Lock Toggle.

Each time the NUM LOCK key is pressed the Num Lock toggle bit (bit 5 of RAM location 0:417) is inverted. Note that pressing one of the keypad keys while a shift key is down inverts the state of the numlock and the token inserted into the buffer will be the opposite to that which Num Lock indicates. (ie. Num Lock light off + [Shift] gives one of the keypad numeric keys).

9. [Alt]+[Numeric Key Pad 0 to 9]: Absolute Key Token.

When the [Alt] key is held down, an absolute key token may be entered via the numeric keypad. Pressing any other key resets the absolute key token to zero (and inserts the associated Alt-key token for the key pressed). When [ALT] is released the absolute key token modulo 256 is placed into the keyboard buffer, unless the token is zero, in which case it is discarded.

10. [Alt], [Ctrl], [Shift], [Caps Lock] & [Num Lock].

The translation of various key codes into their respective tokens is affected by the current states of these keys (which is stored in location 00417). The [Shift] key, while pressed, reverses the current state of the Caps Lock and Num Lock. If more than one of Alt, Ctrl, Shift, Num Lock or Caps Lock is active at one time then the order of precedence for key code translation is Alt, then Ctrl, then Shift, then Caps Lock or Num Lock.

Caps Lock, when active, converts the key tokens for the lower case alphabetic keys (a - z) to their upper case counterparts.

Note that some programs (such as KEYB) install their own entry points into the interrupt vectors and these interrupt routines may exhibit different characteristics than those of the ROS routines described here.

2.3.5 Interrupt 14: Floppy Disk Controller (0Eh).

The ROS service routine for interrupt 14 sets bit 7 of the RAM DRIVE RESTORE FLAG, to indicate that the Floppy Disk Controller interrupt has occurred.

CPU registers are used as follows:

Entry:

No conditions.

Exit:

All flags and registers preserved.

2.3.6 Interrupt 16: Video I/O (10h).

The ROS interrupt 16 service routine provides a set of routines for reading and writing characters in alpha and graphics mode. In graphics mode the characters are constructed using a character matrix table (see section 2.3.20). It also provides facilities for scrolling the screen up or down, reading and writing pixels (graphics only) and reading the light pen.

CPU registers for Video Int 16 are used as follows:

Entry:

AH = Function Selector as follows:

• 0 - Set Video Mode.
• 1 - Set Cursor Size.
• 2 - Set Cursor Address.
• 3 - Get Cursor Address.
• 4 - Get Light Pen Address.
• 5 - Set Display Page.
• 6 - Scroll Screen Up.
• 7 - Scroll Screen Down.
• 8 - Read Character and Attributes.
• 9 - Write Character and Attributes.
• 10 - Write Character only (0Ah).
• 11 - Write Colour Select Register (0Bh).
• 12 - Write Pixel (0Ch).
• 13 - Read Pixel (0Dh).
• 14 - Write Character in Teletype Emulation mode (0Eh).
• 15 - Get Video Parameters (0Fh).

All other registers as required by the function.

Exit:

If selector is greater than 15 then carry is set, else carry is clear.

All other flags and registers as specified by the function.

Alpha modes 0 and 1 require 2000 bytes of video RAM while alpha modes 2 and 3 require 4000 bytes of the video RAM. The ROS takes advantage of all the video RAM available in alpha modes by supporting multiple display pages. This means that application programs can set up a number of display pages and switch them as required.

In general parameters passed to ROS routines are not checked and care should be taken when choosing unusual parameters as unexpected results may occur. In particular be careful of boundary conditions such as setting the top of the display window equal to the bottom of the display window (for functions 6 and 7) effectively creating a one line display. In this instance the screen scrolling may not perform as expected.

Int 16 Function 0: Set Video Mode.

CPU registers are used as follows:

Entry:

AH = 0
AL = Mode Selector as follows:

0 - Alpha 25 Rows by 40 Columns.
1 - Same as Mode 0.
2 - Alpha 28 Rows by 80 Columns.
3 - Same as mode 2.
4 - Graphics 200 pixels by 320 pixels using palette 1.
5 - Graphics 200 pixels by 320 pixels using palette 2.
6 - Graphics 200 pixels by 640 pixels - 2 colours.
7 - Alpha 25 Rows by 80 Columns Monochrome.

Exit:

All flags and registers preserved.

In mode 4 palette 0 may be selected by writing the colour select register using Video Int 16 Function 11. The definition of the palettes is contained in Section 1.11.2.1, Graphics Mode 1.

When mode 5 is selected it must be followed by a selection of palette zero (Colour select register - See 1.11.5.2) in order to enable palette 2.

If the default display mode indicates an external monochrome adapter, then mode 7 is selected regardless of the mode in AL.

If the MS bit of System RAM variable location 0:412 is set (80h) then when a mode change into text mode is setup the hardware LCD inverse bit will be set in the mode register and if the display is the internal LCD then the character output will be inverted as described in section 1.11.1.

To select the Video mode the ROS does the following:

1. Disable video output.
2. Reset the Cursor Addresses for all pages to row 0 column 0.
3. Output the mode to the Video mode select register.
4. Reload the 6845 CRTC registers from the Video parameter table (which is supplied by interrupt 31).
5. Clear the video RAM. If an alpha mode is selected, the video RAM is filled with white space, i.e. ASCII space (020h) and the default attribute byte (07 - white). The graphics mode fill is zeros.

6. If colour display then set up the Colour Select register (3D9h):

   Set the border colour to the default background colour.
   In graphics modes set intensified foreground colours.
   In mode 6 (Graphics 640 Mode) set white foreground colour.

7. For text modes select page zero.
8. Set the cursor size to start cursor from the video parameter table.
9. Enable video output.

Int 16 Function 1: Set Cursor Size.

This function is only relevant in alpha modes as the hardware cursor is not supported in graphics modes. It sets the start and end scan numbers of the cursor.

CPU registers are used as follows:

Entry:

AH = 1
CH = Starting scan of cursor in range 0 to 63.
CL = Ending scan of cursor in range 0 to 31.

Exit:

All flags and registers preserved.

Note that values greater than 31 turn the cursor off. This is because bit 5 in the start register is the 6845 cursor off bit.

Int 16 Function 2: Set Cursor Address.

This function sets the current row and column addresses of the cursor in the specified page.

CPU registers are used as follows:

Entry:

AH = 2
BH = Page number for modes 0 to 3.

• (Must be zero for all other modes.)

DH = Cursor Row Address.
DL = Cursor Column Address.

Exit:

All flags and registers preserved.

Refer to section 1.11.4 (BIOS Modes) for valid page numbers and page starting address details.

Int 16 Function 3: Get Cursor Address.

This function returns the current row and column address of the cursor in the specified page.

CPU registers are used as follows:

Entry:

AH = 3
BH = Page number for modes 0 to 3.

• (Must be zero for all other modes.)

Exit:

DH = Cursor Row Address.
DL = Cursor Column Address.
CH = Starting scan of cursor.
CL = Ending scan of cursor.
All flags and other registers preserved.

Refer to section 1.11.4 for valid page numbers and page starting address details.

Int 16 Function 4: Get Light Pen Address.

This function returns the address of the light pen.

CPU registers are used as follows:

Entry:

AH = 4.

Exit:

If Light Pen switch set then

• AH = 1.
• DH = Character Row address (0 to 24).
• DL = Character Column address (0 to 79).
• CH = Pixel Row address (0 to 199).
• BX = Pixel Column address (0 to 639).

If Light Pen switch clear then

• AH = 1.
• BX, CH & DX preserved.

Always

• All flags and other registers preserved.

Int 16 Function 5: Set Display Page.

This function sets the active display page.

CPU registers are used as follows:

Entry:

AH = 5.
BH = Page number to be displayed.

Exit:

All flags and registers preserved.

Refer to section 1.11.4 for valid page numbers and page starting address details.

Int 16 Function 6: Scroll Screen UP.

This function scrolls the active display page, or part of the active display page up a specified number of lines.

CPU registers are used as follows:

Entry:

AH = 6.
DH = Bottom Row of area to scroll.
DL = Right most Column of area to scroll.
CH = Top Row of area to scroll.
CL = Left most Column of area to scroll
BH = Attributes for blank lines scrolled onto the bottom of the scroll area.
AL = Number of lines to roll up.

• If AL = 0 then blank the specified area.
• If AL not zero then roll specified area up by the number of lines in AL.
• If DH = CH then AL must be zero.

Exit:

All registers preserved.
Carry is clear and all other flags corrupt.

Scrolling always takes effect on the current active display page.

Hardware scrolling is not supported. Scrolling is achieved by copying areas of Video Display RAM.

In graphics modes blank lines are filled with zeros to display the current background colour.

Note this function will fail to operate properly if on entry CH equals DH and AL is not zero. This is also true for all other compatible ROM environments.

Int 16 Function 7: Scroll Screen down.

This function scrolls the active display page, or part of the active display page down a specified number of lines.

CPU registers are used as follows:

Entry:

AH = 7.
DH = Bottom Row of area to scroll.
DL = Right most Column of area to scroll.
CH = Top Row of area to scroll.
CL = Left most Column of area to scroll
BH = Attributes for blank lines scrolled onto the top of the scroll area.
AL = Number of lines to roll down.

• If AL = 0 then blank the specified area.
• If AL not zero then roll specified area down by the number of lines in AL.
• If DH = CH then AL must be zero.

Exit:

All flags and registers preserved.

Scrolling always takes effect on the current active display page.

Hardware scrolling is not supported. Scrolling is achieved by copying areas of Video Display RAM.

Note this function will fail to operate properly if on entry CH equals DH and AL is not zero.

Int 16 Function 8: Read Character and Attributes.

This function reads the character and its associated attribute byte at the current cursor address in a specified display page.

In graphics modes, the character pixel data is generated either from an internal character matrix table for characters 0 to 127 or from an external character matrix table for characters 128 to 255, the address of which is held in interrupt vector 31. See 2.3.20 for additional details.

CPU registers are used as follows:

Entry:

AH = 8.
BH = Page to read for alpha modes 0 to 3.

• (Must be zero for all other modes.)

Exit:

AL = Character. (0 if no match found in Graphics Modes).
AH = Attributes byte. (Unchanged in graphics modes).
All flags and registers preserved.

Refer to 1.11.1 and 1.11.2 for the definition of the character attributes bytes.

Int 16 Function 9: Write Character and Attributes.

This function writes a character (or a block of the same character) and its associated attribute byte to the current cursor position in a specified display page.

In graphics modes, the character pixel data is generated either from an internal character matrix table for characters 0 to 127 or from an external character matrix table for characters 128 to 255, the address of which is held in interrupt vector 31. See 2.3.20 for additional details.

CPU registers are used as follows:

Entry:

AH = 9.
AL = Character to write.
BH = Page to write for alpha modes 0 to 3.

• (Must be zero for all other modes.)

BL = In alpha modes

• Attributes of character.

In graphic modes

• Write mode as follows:
  • Bit 7 = 0 for character overwrite mode.
  • Bit 7 = 1 for character XOR mode.
  • Bits 0 and 1 = required character colour (for modes 4 & 5 only).

CX = Repeat Count.

Exit:

All flags and registers preserved.

The repeat count specifies the number of consecutive locations to which the character and attributes are written. In graphics modes all characters must fit on the current line.

In graphics mode if bit 7 of BL is set then the data for the specified character is exclusive ORed with the data already in the display RAM at the cursor address.

Int 16 Function 10: Write Character Only.

This function writes a character (or a block of the same character) to the current cursor position in a specified display page. In alpha modes the attribute bytes for all characters written remains unchanged.

In graphics modes, the character pixel data is generated either from an internal character matrix table for characters 0 to 127 or from an external character matrix table for characters 128 to 255, the address of which is held in interrupt vector 31. See 2.3.20 for additional details.

CPU registers are used as follows:

Entry:

AH = 10 (0Ah).
AL = Character to write.
BH = Page to write for alpha modes 0 to 3.

• (Must be zero for all other modes.)

BL = In alpha modes

• BL is not used.

In graphic modes

• Write mode as follows:
  • Bit 7 = 0 for character overwrite mode.
  • Bit 7 = 1 for character XOR mode.
  • Bits 0 and 1 = required character colour (for modes 4 & 5 only).

CX = Repeat Count.

Exit:

All flags and registers preserved.

The repeat count specifies the number of consecutive locations to which the character is written.

In graphics mode if bit 7 of BL is set then the data for the specified character is exclusive ORed with the data already in the display RAM at the cursor address.

Int 16 Function 11: Write Colour Select Register.

This function writes the CGA compatible Colour Select Register IRGB bits or the Palette select bits.

CPU registers are used as follows:

Entry:

AH = 11 (0Bh).
BH = Function select:

• Zero - Set the IRGB bits (3-0) as specified by BL.
• Non Zero - Set the Palette (0 or 1) as specified by BL.

Exit:

All flags and registers preserved.

Changing the palette number (BH non-zero) only has effect in modes 4 and 5 (320 pixel graphics mode). Refer to section 1.11.3 for further details.

Int 16 Function 12: Write a Pixel.

This function writes an individual pixel (only valid in graphics modes).

CPU registers are used as follows:

Entry:

AH = 12 (0Ch).
DX = Pixel Row (0 to 199)
CX = Pixel Column (0 to 639)
AL = Write Mode:

• Bit 7 = 0 for character overwrite mode.
• Bit 7 = 1 for character XOR mode.
• Bits 0 & 1 = Character Colour for 320 graphics modes.

Exit:

All flags and registers preserved.

The pixel colour specified in AL should be in the range 0 to 3 in modes 4 and 5 (graphics 320 pixel mode) and in the range 0 to 1 for mode 6 (graphics 640 pixel mode).

Int 16 Function 13: Read a Pixel.

This function is used for reading an individual pixel (only in graphics modes).

CPU registers are used as follows:

Entry:

AH = 13 (0Dh).
DX = Pixel Row (0 to 199)
CX = Pixel Column (0 to 639)

Exit:

AL = Colour of the specified pixel.
All flags and other registers preserved.

Int 16 Function 14: Write in TTY Emulation Mode.

This function writes the specified character in Teletype emulation mode at the current cursor address in the active display page.

CPU registers are used as follows:

Entry:

AH = 14 (0Eh).
AL = Character to write.
BL = In alpha modes

• BL is not used.

In graphic modes

• Write mode as follows:
  • Bit 7 = 0 for character overwrite mode.
  • Bit 7 = 1 for character XOR mode.
  • Bits 0 and 1 = required character colour (for modes 4 & 5 only).

Exit:

All flags and registers preserved.

Upon completion of the write the cursor column is incremented by one. If the column address is greater than the line length then the column address is set to zero and the cursor row address is incremented by one.

If the incremented row address is greater than the last visible line then it is decremented to its original value and the entire page is scrolled up one line. In alpha modes the line added to the bottom of the page is cleared to spaces with the attributes the same as the first character in previous line. In graphic modes the bottom line is cleared to zeroes.

The following display characters are executed rather than displayed symbolically:

BEL (07h)

Sounds a short (bleep) tone on the speaker.

BS (08h)

Decrements the cursor column one character position unless the column is already zero in which case it is ignored.

CR (0Dh)

Sets the cursor column address to zero.

LF (0Ah)

Increments the cursor row address by one and follows the scroll up procedure as detailed in the paragraph above.

All other control characters are displayed.

Int 16 Function 15: Get Current Video Parameters.

This function returns the current Video Mode, the current display page and number of visible columns.

CPU registers are used as follows:

Entry:

AH = 15 (0Fh).

Exit:

BH = Current active display Page (or zero if in graphics modes or alpha mode 7).
AH = Number of visible columns (40 or 80).
AL = Current video mode (0 to 7).

All flags and other registers preserved.

2.3.7 Interrupt 17: System Configuration (11h).

This software interrupt returns the current system configuration status ad defined in RAM locations 0:410 and 0:411 hex (see section 2.4).

CPU registers are used as follows:

Entry:

No conditions.

Exit:

AX = System Configuration status:

All flags and other registers preserved.

Section 1.8.2 (Port A - Status-1 Input) contains the default mode states as defined in the DDM1 and DDM0 bits.

2.3.8 Interrupt 18: Memory Size (12h).

This software interrupt returns the system RAM size as held in system locations 0:413 and 0:414 hex.

CPU registers are used as follows:

Entry:

No conditions.

Exit:

AX = Number of 1K memory blocks fitted.
All flags and other registers preserved.

2.3.9 Interrupt 19: Disk I/O (13h).

This software interrupt provides disk read, write, verify, and format functions for the drives fitted to the standard floppy disk controller.

In actual practice by the time the MS-DOS operating system has been loaded and an applications program is activated, the DOS startup process will have saved the ROS's interrupt vector (from location 0:4Ch) and installed its own entry vector. DOS does this so that it can correct for such conditions as DMA over a 64K segment boundary and it will break this sort of I/O requrest into a number of smaller I/O requests. In addition any installed hard disk will have 'chained' itself into the interrupt 19 vector so that requests with the MSB of the drive number set can be serviced by its ROM based hard disk I/O routines (usually in the C8000h address range). In general the call parameters for the hard disks are the same as those described here for read and write, however there are a number of additional services provided by the hard disk BIOS ROM's. The hard disk error return codes are also somewhat extended to the floppy disk group documented here. The typical 'compatible' hard disk function selector list and errors are documentedd following the ROS's functions.

CPU registers are used as follows:

Entry:

AH = Disk I/O Function selector:

• 0 - Initialise the disk sub-system.
• 1 - Return the status of the last operation.
• 2 - Read a number of consecutive sectors.
• 3 - Write a number of consecutive sectors.
• 4 - Verify a number of consecutive sectors.
• 5 - Format a track.
• 8 - Read Drive parameters.
• 21 - Read Drive Type (15h).
• 22 - Read Disk Change Status (16h).

Exit:

AH = Status Byte:

• 0 - Operation completed successfully.
• 1 - Incorrect function (or drive) specifier.
• 2 - Missing address mark error.
• 3 - Disk write protected (Write or Format commands only).
• 4 - Record not found.
• 8 - DMA overrun error.
• 9 - Attempted DMA over a 64K segment boundary.
• 16 - CRC error (10h).
• 32 - Floppy disk controller error (20h).
• 64 - Seek error (40h).
• 128 - Floppy disk controller timeout (Drive Not Ready) (80h).

All other registers as specified by the selected function.

For all disk functions the Carry Flag (CY) will be clear if no error else it is set if an error (and AH = error number). All other flags are corrupt.

For all disk functions except 0 & 1 drive number (DL) is checked and if greater than maximum drive number the function is rejected and return status is set to 1 (AH=1) and carry is set.

Media changed error status is only applicable to operations which transfer information to and from the magnetic media. It is derived using the following procedure: Before performing the I/O operation the selected disk drive's change line status is checked. If false then the I/O operation carries on as normal. If, however the change line is active then the ROS attempts to clear the change line by issuing a step pulse. If the change status clears then there is media installed and the door is closed and the I/O operation terminates by reporting that change line was detected. (AH = 06). If however the change line remains true then either the door is open or there's no diskette installed (or both) and in this case a timeout error (AH = 128) is returned.

Disk Function 0: Initalise Disk Sub-System.

This function performs a total initialisation of the disk interface as follows:

1. Reset the FDC (Floppy Disk Controller).
2. Re-configure the FDC parameters to those specified in the disk parameter table (see interrupt 30).

CPU registers are used as follows:

Entry:

AH = 0.

Exit:

AH/Flags = Status as specified above.
All registers preserved.

When an error is returned by any other disk I/O function, the Initialise Disk function should be called prior to the next disk I/O operation.

Disk Function 1: Return Last Status.

This function returns the status byte and Carry Bit of the last disk I/O operation.

CPU registers are used as follows:

Entry:

AH = 1.

Exit:

AH/Flags = Status of last disk I/O as specified above.
All other registers preserved.

Disk Function 2: Read Sector.

This function reads a number of consecutive sectors. All sectors to be read must be on the same track.

CPU registers are used as follows:

Entry:

AH = 2.
DH = Head Number (0 or 1).
DL = Drive Number (0 or 1).
CH = Track Number.
CL = Starting Sector Number.
BX = Offset Address of Read Data Buffer.
ES = Segment Address of Read Data Buffer.
AL = Number of Sectors to Read.

Exit:

AH/Flags = Status as specified above.
AL = Number of Sectors successfully read.

• (Corrupt if Timeout error.)

All other registers preserved.

Disk Function 3: Write Sector.

This function writes a number of consecutive sectors. All sectors to be written must be on the same track.

CPU registers are used as follows:

Entry:

AH = 3.
DH = Head Number (0 or 1).
DL = Drive Number (0 or 1).
CH = Track Number.
CL = Starting Sector Number.
BX = Offset Address of Write Data Buffer.
ES = Segment Address of Write Data Buffer.
AL = Number of Sectors to Write.

Exit:

AH/Flags = Status as specified in 2.3.9.
AL = Number of Sectors successfully written.

• (Corrupt if Timeout error.)

All other registers preserved.

Disk Function 4: Verify Sector.

This function verifies a number of consecutive sectors. All sectors to be verified must be on the same track.

CPU registers are used as follows:

Entry:

AH = 4.
DH = Head Number (0 or 1).
DL = Drive Number (0 or 1).
CH = Track Number.
CL = Starting Sector Number.
AL = Number of Sectors to Verify.

Exit:

AH/Flags = Status as specified above.
AL = Number of Sectors successfully verified.

• (Corrupt if Timeout error.)

All other registers preserved.

Since the verification process is halted upon the first occurrence of an error, AL represents the number of sectors successfully verified prior to the occurrence of an error or total sectors verified if no error.

Disk Function 5: Format Track.

This function formats an entire track.

CPU registers are used as follows:

Entry:

AH = 5.
DH = Head Number (0 or 1).
DL = Drive Number (0 or 1).
CH = Track Number.
BX = Offset Address of Format Buffer.
ES = Segment Address of Format Buffer.

Exit:

AH/Flags = Status as specified above.
All other registers preserved.

The format buffer contains four bytes of information for each sector on the track:

1. Track Number.
2. Side Number.
3. Sector Number.
4. Sector Size Code:
   • 0 - 128 bytes / Sector.
   • 1 - 256 bytes / Sector.
   • 2 - 512 bytes / Sector.
   • 3 - 1024 bytes / Sector.

The gap length, filler byte and sectors per track required by the FDC Format command are obtained from the DPT (See Disk Parameter Table - Section 2.3.20).

Disk Function 8: Read Drive Parameters

This function returns the floppy disk drive parameters.

CPU registers are used as follows:

Entry:

AH = 8.
DL = Drive Number (0 or 1).

Exit:

AX = 0
DH = Number of Heads - 1. (1)
DL = Number of Drives installed. (1 or 2)
CH = Number of Tracks - 1. (79)
CL = Number of Sectors per Track. (9)
ES:DI = 20-bit pointer to Disk Parameter Table for the drive.
Flags corrupt and CY clear.
All other registers preserved.

Disk Function 21: Read Drive Type

This function returns the floppy disk drive type.

CPU registers are used as follows:

Entry:

AH = 21 (15h).
DL = Drive Number (0 or 1).

Exit:

AH = 2 (Diskette with change line.)
Flags corrupt and CY clear.
All other registers preserved.

Disk Function 22: Read Disk Changeline.

This function returns the drive changeline status.

CPU registers are used as follows:

Entry:

AH = 22 (16h).
DL = Drive Number (0 or 1).

Exit:

AH = 0 if change line not active & CY clear.
6 if change line active & CY set.
Flags corrupt and CY as above
All other registers preserved.

Note that this function does not clear the change line signal. An I/O function must be performed to clear change line active.

Hard Disk Call parameters and registers.

As explained in the beginning of the ROS's floppy disk Int 19 calls, the 'compatible' hard disk expansion slot ROM supports a register interface similar to the floppy disk I/O but with extended functions required for the hard disk environment. This section gives the setup registers for this 'compatible' hard disk I/O call.

CPU registers are used as follows:

Entry:

AH = Hard Disk I/O Function selector:

• 0 - Reset Controller.
• 1 - Return the status of the last operation.
• 2 - Read a number of consecutive sectors.
• 3 - Write a number of consecutive sectors.
• 4 - Verify a number of consecutive sectors.
• 5 - Format a track.
• 6 - Format a track with bad sector markers.
• 7 - Format the entire drive.
• 8 - Return drive parameters.
• 9 - Set drive parameters.
• 10 - Read Long.
• 11 - Write Long.
• 12 - Seek to Track.
• 13 - Reset Controller (Alternate Entry).
• 14 - Read Sector Buffer.
• 15 - Write Sector Buffer.
• 16 - Test Drive ready.
• 17 - Recalibrate Seek.
• 18 - Ram Diagnostic.
• 19 - Drive Diagnostic.
• 20 - Controller Diagnostic.
• 22 - Park Heads over the landing zone.

Exit:

AH = Status Byte:

• 0 - Operation completed successfully.
• 1 - Incorrect function (or drive) specifier.
• 2 - Missing address mark error.
• 4 - Record not found.
• 7 - Drive initialization failure.
• 8 - DMA overrun error.
• 9 - Attempted DMA over a 64K segment boundary.
• 11 - Bad Track marker detected (0Bh).
• 16 - ECC error (10h).
• 17 - ECC data corrected (11h).
• 32 - Hard disk controller error (20h).
• 64 - Seek error (40h).
• 128 - Disk controller timeout (Drive Not Ready) (80h).
• 187 - Undefined error occurred (BBh).
• 255 - Read Status Failure (FFh).

The register call parameters for the function selections are very similar to the equivalent floppy disk I/O calls and are typically as follows:

Function Selector

AH: 0 - 20 & 22 (as per the table above)

Sector Count

AL: 1 - n. (17 Sectors / Track - typical)

Interleave Factor

AL: 1 - 16 Typically 3 to 7 (for the formatting calls)

Drive Number

DL: 80h - FFh (Drive C: is 80h, D: is 81h ... etc).

Sector Number

CL: 1 - 17 (Lower 6 bits of CL).

Head Number

DH: 0 - n (Typically 3 for 20MB drives with 4 heads).

Cylinder Number

CH: 0 - 1023 (8 LS Bits and 2 additional MS bits in the upper 2 MS bits of CL).

Buffer Address

ES:BX --> Segment:Offset value.

Exit:

AH: Return status as listed in the above table.
CF: Carry Flag Clear - No errors. (AH = 0)
Carry Flag Set - Error ccode in AH.

When Drive parameters are requested (Function 8) the return registers are as follows:

Hard disk drive count

DL. (1 to n)

Maximum Head Number

DH. (0 to n-1)

Sectors per Track

CL. (bits 0 - 5)

Maximum Cylinder Number

CH. (10 bits: 8 LSBs in CH and 2 MS bits in the 2 upper bits of CL).

Cylinders and heads are numbered starting from zero, therefore the max numbers are 'n-1'. Sectors are numbered starting at 1 and go to n which is typically 17 for the current 'MFM' technology. Newer 'RLL' technology drives are beginning to appear with 26 sectors per track. The maximum track number is actually one higher than the number reported but the highest track (termed the maintenance cylinder) is reserved for diagnostic software maintenance tests so that applications cannot use this track for storage.

Setting bad track markers is the method used to force DOS to set its 'Bad Sector Markers' during the logical formatting process.

Hard disk formatting is a confusing subject because there are two formatting passes necessary before the disk is ready for usage. The first formatting required is the low level (hard) formatting process which writes the actual sector ID fields on the media. When a hard disk is being prepared for usage by MS-DOS it must then be partitioned (using the FDISK utility) and finally 'Logically Formatted' the using the MS-DOS FORMAT utility. MS-DOS formatting is merely a quick once over verify process to find any areas which are not readable and for which it will mark the unreadable blocks in the DOS File Allocation Table (FAT). MS-DOS then installs its file directory and FATs on the disk and reports disk size and bad sector counts. The initial hard formatting process is a factory process which must take place in a controlled environment (temperature and etc.) and the manufacturer's media defect list is entered and bad tracks marked. User attempts to format hard disks are fraught with difficulties usually because of the media defect problem whereby areas which may appear readable to MS-DOS's formatter but which fail to retain certain data patterns contained in actual data written later and these will cause 'Unrecoverable Read Error' reports to appear and frustrate all concerned. It is generally a good idea to leave the debugger 'g=C800:5' ROM formatter entry point to the experts.

2.3.10 Interrupt 20: Serial I/O (14h).

This software interrupt provides functions for character I/O to one of the two serial channels and functions for configuring the serial parameters.

Two channels are supported, logical serial device 0 (COM1:) which is always configured and logical serial device 1 (COM2:) which is optional. Power-up initialisation determines whether serial device 1 is installed.

CPU registers are used as follows:

Entry:

AH = Serial I/O function selector:

• 0 - Initialise Serial Port.
• 1 - Write Character to Serial Port.
• 2 - Read Character from Serial Port.
• 3 - Return status of Serial Port.

DX = Logical Channel Number (0 or 1).
All other registers as required by the specified function.

Exit:

AX = Returned Status/Character as defined by the function.
All flags and other registers preserved.

If logical channel number is out of range (greater than 1) or is not fitted then the function is abandoned and the timeout error status (bit 7 of AH) is returned and all other bits in AX are undefined.

The Logical Serial Device Timeout Count RAM variables (locations 0047C & 0047D) specify the time out delay (in half seconds) used for channel timeout. See section 2.4.

Serial Function 0: Initalise Port.

This function performs a complete reinitialisation of a serial channel. Setting the Baud Rate, Data Bits, Stop Bits and Parity.

CPU registers are used as follows:

Entry:

AH = 0.
DX = Logical Channel Number (0 or 1).
AL = Hardware configuration:

Exit:

AH = 8250 Line Status register (See section 3.4).
AL = 8250 Modem Status register.
All flags and other registers preserved.

The Baud Rate code (bits 5 thru 7) is one of the following:

• 0 - 110 Baud.
• 1 - 150 Baud.
• 2 - 300 Baud.
• 3 - 600 Baud.
• 4 - 1200 Baud.
• 5 - 2400 Baud.
• 6 - 4800 Baud.
• 7 - 9600 Baud.

If the hardware flow control bit in the NVR default VDU mode byte is set then RTS is raised true and DTR is set false. Otherwise the current state of the control lines is preserved.

Serial Function 1: Send Character.

This function performs a character out sequence to the selected port. The character is output when CTS and the 8250 Tx Holding Register Empty status is also true. If the character cannot be sent within the time specified in the logical serial device timeout count RAM variable then the command is abandoned and AH is returned with bit 7 set.

CPU registers are used as follows:

Entry:

AH = 1.
AL = Character to be sent.
DX = Logical Channel Number (0 or 1).

Exit:

AH = 8250 Line Status register bits 0 to 6. Bit 7 is set if the channel timed out else bit 7 is clear and the character was sent.

All flags and other registers preserved.

When this function is called, RTS is raised true.

Upon exit both the RTS and DTR control lines are left in their current state.

The Logical Serial Device Timeout Count RAM variables (locations 0:47C and 0:47D) specify the time out delay (in half seconds) used for channel timeout.

Serial Sub-Function 2: Read Character.

This function attempts to read a character from the specified serial port. The character is not read until both Data Ready (DR) and Data Set Ready (DSR) status bits are both true. If a character is not received within the time specified by the logical device timeout count then the command is abandoned and timeout status is flagged.

CPU registers are used as follows:

Entry:

AH = 2.
DX = Logical Channel Number (0 or 1).

Exit:

If character received from 8250 then
AL = Character received.
AH = Character status:

If logical channel timed out then

• AH = 080h (bit 7 = 1).

Always

• All flags and other registers preserved.

If the character is received with no errors then AH = 0 on exit.

Upon entry, if no character is available at the serial port DTR is set in the Modem Control Register.

If logical channel number is out of range or is not fitted then the function is abandoned and the timeout error status (bit 7 of AH) is returned and all other bits in AX are undefined.

The Logical Serial Device Timeout Count RAM variables (locations 0:47C and 0:47D) specify the time out delay (in half seconds) used for channel timeout.

Serial Function 3: Get Channel Status.

This function returns the status of the specified logical channel.

CPU registers are used as follows:

Entry:

AH = 3.
DX = Logical Channel Number (0 or 1).

Exit:

AH = 8250 Line Status register (See section 3.4).
AL = 8250 Modem Status register.
All flags and other registers preserved.

All flags and other registers preserved.

If logical channel number is out of range or is not fitted then the function is abandoned and the timeout error status (bit 7 of AH) is returned and all other bits in AX are undefined.

2.3.11 Interrupt 22: Keyboard I/O (16h).

This software interrupt provides access to the keyboard buffer and the current toggle status.

CPU registers are used as follows:

Entry:

AH = Keyboard I/O function selector.

• 0 - Get key token from the keyboard buffer.
• 1 - Return keyboard buffer status.
• 2 - Return current key toggle and key States.
• 5 - Insert token into keyboard buffer.
• 16 - Get extended key token from the keyboard buffer (10h).
• 17 - Return extended keyboard Buffer status (11h).
• 18 - Return extended control states (12h).

Exit:

If function selector out of range then

• AH = AH - 18.

If function within range then

• All flags and registers as specified by function.

Keyboard I/O Function 0: Get Key Token.

Return the next non-extended key token from the key token buffer. If no non-extended key token is available then wait until a key token is available. If an extended key token is encountered during the token search it is discarded. The key token search is carried out as follows:

If high byte of the token equals 00

then return the token. (Alt keypad token)

If high byte of the token is greater than 84h

then discard the token.

If low byte of the token equals F0h

then discard the token.

If low byte of the token equals E0h

then set the low byte 00h and return entry.

All other entries are returned unchanged except for:

• E00Dh (Key Pad - Enter) translated to 1C0Dh (Enter).
• E02Fh (Key Pad - Slash) translated to 352Fh (Slash).

CPU registers are used as follows:

Entry:

AH = 0.

Exit:

AX = Key Token.
All flags and other registers preserved.

Keyboard I/O Function 1: Return Keyboard Buffer Status.

Test whether the key token buffer is empty. If it is not empty return the next key token to be taken out of the buffer without removing it from the buffer.

This sub-function uses the same process as sub-function 0 to determine whether there is a non- extended key token in the keyboard buffer. Extended tokens are discarded in the key token search process.

CPU registers are used as follows:

Entry:

AH = 1.

Exit:

If key token buffer is empty then

• Zero flag true.
• AX corrupt.

If one or more tokens in buffer then

• Zero flag false.
• AX = next key token to be removed from buffer.

Always

• Interrupts enabled.
• All other flags corrupt.
• All other registers preserved.

Keyboard I/O Function 2: Return Shift States.

Return the current value of the shift states (from 0:417h).

CPU registers are used as follows:

Entry:

AH = 2.

Exit:

AL = Current shift states:

All flags and other registers preserved.

Keyboard I/O Function 5: Insert token into keyboard buffer.

Insert 16-bit key token into the keyboard buffer.

CPU registers are used as follows:

Entry:

AH = 5.
CX = Token to be inserted into the buffer.

Exit:

AL = 0: Insertion Successful
AL = 1: Keyboard Buffer Full - Token discarded.
All flags and other registers preserved.

Keyboard I/O Function 16: Get Extended Key Token.

Return the next key token from the key token buffer, if buffer empty then waits till one is available.

The key token translation process is as follows:

If low byte of the token equals F0h

then set the low byte 00h and return entry.

All other key tokens are returned unchanged.

CPU registers are used as follows:

Entry:

AH = 16 (10h).

Exit:

AX = Key Token.
All flags and other registers preserved.

Keyboard I/O Function 17: Return Extended Keyboard Buffer Status.

Test whether the key token buffer is empty. If it is not empty return the next key token to be taken out of the buffer without actually removing it.

This sub-function uses the same process as sub-function 16.

CPU registers are used as follows:

Entry:

AH = 17 (11h).

Exit:

If key token buffer empty then

• Zero flag true.
• AX corrupt.

If one or more tokens in buffer then

• Zero flag false.
• AX = next key token to be removed from buffer.

Always

• Interrupts enabled.
• All other flags corrupt.
• All other registers preserved.

Keyboard I/O Function 18: Return Extended Shift States.

Returns two bytes relating to the state of system ram locations 417h, 418h and 496h which contain keyboard status information.

CPU registers are used as follows:

Entry:

AH = 18 (12h).

Exit:

AX = Current extended shift states:

AH Register -

AL Register -

2.3.12 Interrupt 23: Printer I/O (17h).

This software interrupt provides access to the three printer channels.

CPU registers are used as follows:

Entry:

AH = Printer I/O Function selector:

• 0 - Send character to printer port.
• 1 - Initialise printer port.
• 2 - Return printer port status.

DX = Logical Channel Number (0 - 2).
Other registers as specified by function.

Exit:

AH = Printer Port Status (Bits 1 - 7):

All flags and other registers preserved.

Three logical channels are supported. Logical printer device 0 is the system port and is standard to all machines. The power-up initialisation sequence determines if additional external printer ports are present. When both additional printer interfaces are present, device 1 is the external printer port and device 2 is the printer port on the external monochrome VDU controller. If only one additional printer interface is present it is always logical device 1.

Locations 0478h - 047Ah contain the Logical Printer Device timeout counts (see section 2.4).

Printer Function 0: Print Character.

This function attempts to output a character to the specified printer port. If the character cannot be sent within the time specified by the logical printer timout count RAM variable then the command is abandoned and AH is returned with bit 0 set.

CPU registers are used as follows:

Entry:

AH = 0.
AL = Character to be printed.
DX = Logical Channel Number (0 - 2).

Exit:

AH = Printer Port status (as given above) or Timeout (Bit 0) set.
All flags and other registers preserved.

Printer Function 1: Initialise Printer Channel.

This function performs a complete reinitialisation of a specified printer channel (if present). The printer INIT signal is held low for approximately 4 milliseconds. Printer interrupts and auto linefeed are disabled.

CPU registers are used as follows:

Entry:

AH = 1.
DX = Logical Channel Number (0 - 2).

Exit:

AH = Printer Port status (as given above) or Invalid Channel (Bit 0) set.
All flags and other registers preserved.

Printer Function 2: Return Channel Status.

This function returns the status register of the specified logical printer channel (if present).

CPU registers are used as follows:

Entry:

AH = 2.
DX = Logical Channel Number (0 - 2).

Exit:

AH = Printer Port status (as given above) or Invalid Channel (Bit 0) set.
All flags and other registers preserved.

2.3.13 Interrupt 24: System Restart (18h).

If a Hard Disk ROM BIOS was initialized during Power-Up Initialization then it will have installed its entry point into this vector and saved the ROS's vector in its private storage area. Its bootstrap process resembles the process described below (under Int 25) and if successful the system from the active partition of the hard disk will be loaded if not then it executes the ROS's Int 24 whose vector it has saved.

This software interrupt is intended to provide an orderly system restart capability. A message is displayed on the active VDU requesting that the user "Insert a SYSTEM disk into Drive A" and "Then press any key." When the keypress is received, the Disk Bootstrap process (Interrupt 25) is invoked.

CPU registers are used as follows:

Entry:

No conditions.

Exit:

Disk Bootstrap.

2.3.14 Interrupt 25: Disk Bootstrap (19h).

This software interrupt to provide access to the disk bootstrap process which is normally executed after power-up initialisation tests.

The ROS attempts to load the bootstrap sector (from drive A, side 0, track 0, sector 1) into memory at 07C00. If the bootstrap sector is loaded successfully it is given control (far jump to segment 0000 offset 7C00). If the bootstrap sector cannot be loaded after 10 retries, the ROS will display a message prompting the user to "Insert a SYSTEM disk into drive A" and "Then press any key." The ROS then waits for the keypress and repeats the system restart procedure (Int 24).

CPU registers are used as follows:

Entry:

No conditions.

Exit:

To program loaded by Disk Bootstrap.

2.3.15 Interrupt 26: System Clock & Real Time Clock (1Ah).

This software interrupt routine provides access to both the system (software maintained) clock location as well the Real Time Clock (RTC) hardware.

CPU registers are used as follows:

Entry:

AH = Clock Function specifier:

• 0 - Get System Clock.
• 1 - Set System Clock.
• 2 - Get RTC time.
• 3 - Set RTC time.
• 4 - Get RTC date.
• 5 - Set RTC date.
• 6 - Set RTC alarm.
• 7 - Reset RTC alarm.

All other registers as required by function.

Exit:

All registers as specified by function.

Clock Function 0: Get System Clock.

This function returns the current value of the 32 bit system clock value.

CPU registers are used as follows:

Entry:

AH = 0.

Exit:

DX = Least Significant Word of the clock count.
CX = Most Significant Word of the clock count.
AL = 24 Hour Flag:

• 0 if not past 24 hours.
• 1 if past 24 hours.

All flags and other registers preserved.

The 32 but system clock is incremented every 54.9 milliseconds by the ticker hardware interrupt routine. When the count reaches the 24 hour value (0001800B0h) the 24 Hour flag is set and the system clock count is reset to zero. This 24 hour count is based on the system clock 1.19318 MHz divided by the maximum divisor, 65536. This gives an interrupt rate of 54.92549323 Ms which when divided into the number of seconds in 24 hours gives this 24 Hour time value above.

Note that the 24 hour flag is reset to zero after it has been read.

Clock Function 1: Set System Clock.

This function sets the current value of the 32 bit system clock value.

CPU registers are used as follows:

Entry:

AH = 1.
DX = Least Significant Word of the clock count.
CX = Most Significant Word of the clock count.

Exit:

All flags and other registers preserved.

Clock Function 2: Get RTC Time.

This function gets the current time from the Real Time Clock.

CPU registers are used as follows:

Entry:

AH = 2.

Exit:

If RTC not operating then

• Carry True.
• CX DX preserved.

If RTC operating then

• Carry False.
• CH = Hour (BCD).
• CL = Minute (BCD).
• DH = Second (BCD).

Always

• All other flags corrupt.
• All other registers preserved.

Clock Sub-Function 3: Set RTC Time.

This function sets the Real Time Clock time.

CPU registers are used as follows:

Entry:

AH = 3.
CH = Hour (BCD).
CL = Minute (BCD).
DH = Second (BCD).
DL = 1 to enable daylight savings option (otherwise 0).

Exit:

If RTC not operating then

• Carry True.

If RTC operating then

• Carry False.

Always

• All other flags corrupt.
• All other registers preserved.

When the daylight savings option is set it enables two special updates of the current time. On the last Sunday in April, the time increments from 1:59:59 AM to 3:00:00 AM. Also on the last Sunday in October the time increments from 1:59:59 AM to 1:00:00 AM.

Note that this option also disables the alarm function.

Clock Function 4: Get RTC Date.

This function gets the current date from the Real Time Clock.

CPU registers are used as follows:

Entry:

AH = 4.

Exit:

If RTC not operating then

• Carry True.
• CX DX preserved.

If RTC operating then

• Carry False.
• CH = Century (BCD).
• CL = Year (BCD).
• DH = Month (BCD).
• DL = Day Of Month (BCD).

Always

• All other flags corrupt.
• All other registers preserved.

The century byte is set to 19 (BCD) if the year is 80 (BCD) or above otherwise it is set to 20 (BCD).

Clock Function 5: Set RTC Date.

This function sets the Real Time Clock time.

CPU registers are used as follows:

Entry:

AH = 5.
CH = Century (BCD) [Ignored].
CL = Year (BCD).
DH = Month (BCD).
DL = Day of Month (BCD).

Exit:

If RTC not operating then

• Carry True.

If RTC operating then

• Carry False.

Always

• All other flags corrupt.
• All other registers preserved.

Century is ignored and is computed as described in Clock Function 4.

Clock Function 6: Set RTC Alarm.

This function sets the alarm time and arms the Real Time Clock alarm interrupt. The alarm interrupt will occur then the current time matches the alarm time. An application program which uses this function must first write the address of its alarm interrupt routine into interrupt vector 10.

CPU registers are used as follows:

Entry:

AH = 6.
CH = Hour (BCD).
CL = Minute (BCD).
DH = Second (BCD).

Exit:

If RTC alarm already set then

• Carry True.

If RTC alarm not already set then

• Carry False.

Always

• All other flags corrupt.
• All other registers preserved.

Clock Function 7: Kill RTC Alarm.

This function disarms the Real Time Clock alarm function.

CPU registers are used as follows:

Entry:

AH = 7.

Exit:

All flags and registers preserved.

2.3.16 Interrupt 27: Keyboard Break Interrupt (1Bh).

This software interrupt is invoked by the keyboard hardware interrupt routine when a keyboard break ([CTRL] + [NUM LOCK]) is detected.

The power-up initialisation process loads the address of a dummy break handler routine which does an interrupt return (IRET) instruction.

Application programs which supply a keyboard break interrupt must conform to the following register conventions:

Entry:

DS = 0040h (Spanning the ROS data).

Exit:

All registers must be preserved except AX, BX, CX, DX, DS and Flags which may be corrupt.

The supplied interrupt routine must not invoke any other ROS interrupts from within itself but may modify any of the system RAM locations used by the ROS.

2.3.17 Interrupt 28: External Ticker Interrupt (1Ch).

This software interrupt is called from within the System Clock hardware interrupt routine. It is initialised by power-up with a dummy handler which returns from interrupt by doing an IRET instruction. It can be used by application programs which require a process to be run at a regular interval.

Application programs which supply an external ticker interrupt must conform to the following register conventions:

Entry:

DS = 0040h (Spanning the ROS data).

Exit:

All registers must be preserved except AX, DX, DS and Flags which may be corrupt.

The supplied interrupt routine must not invoke any other ROS interrupts from within itself but may modify any of the system RAM locations used by the ROS.

2.3.18 Interrupt 29: VDU Parameter Table (1Dh).

This interrupt vector location contains the 32-bit address of the Video Parameter table used in setting up the 6845 CRTC when changing video mode. Upon power-up or after a reset, the system ROS initialisation process loads the ROM table address into this vector location (0074-0077 hex).

The Video Parameter table consists of four consecutive 16 byte entries. Each entry contains an initialisation quantity for each of the 6845 CRTC registers (See section 1.11.5). When a new video mode is selected the table entry used for initialisation as follows:

The table contains the following initialisation data:

Note that this table reflects industry standard values for CGA and MDA type devices and that at this user level there is no distinction between using the PPC Internal Graphics Adapter and an external (expansion slot based) CGA or MDA. The PPC Auto Switch NMI process will adjust the values loaded into the CRTC to be appropriate to the LCD or external video mode being used. The user can therefore use this table directly without regard to the CRTC initialization values discussed in section 1.11.

2.3.19 Interrupt 30: Disk Parameter Table.

This interrupt vector location contains the 32-bit address of the parameter table of configuration parameters for the disk interface. Upon power-up or after a reset, the initialisation process loads the ROM table address into this vector location (0078 - 007B hex).

The Disk Parameter Table consists of 11 bytes as follows:

2.3.20 Interrupt 31: VDU Matrix Table (1Fh).

This interrupt vector location contains the 32-bit address of the VDU matrix table used in compatible graphics modes for generating pixel data for characters 128 to 255.

Upon power-up or after a reset, the initialisation process loads this vector (007C-007F) with all zeros to indicate that no external VDU matrix table is loaded. Programs such as GRAFTABL.EXE load a resident upper 128 character matrix which can be used in the 640x200 resolution graphics modes.

Each of the 128 character table entries consists of eight bytes, one for each character scan. The first byte is the top scan value and the last byte is the button scan value. The MSB, bit 7, is the left most pixel and the LSB, bit 0, is the right most pixel of the scan. A set bit displays the foreground colour and a reset bit displays the background colour.

2.4 RAM Variables.

The System RAM address space from 00300 to 00500 is used by the ROS for variable storage. The following table lists the variables and their usage. They are either classified as Byte (8-bit), Word (16-bit), Long Word (32-bit) or Buffer (greater than 32-bit) storage locations. Depending on the CPU's segment register setting, the variables at 004xx can be said to be referenced at 40:XXX or 0:4XX.

2.5 Non-Volatile RAM (NVR)

The first 21 bytes of the battery backed RAM within the RTC hardware are for system parameter storage as follows:

Locations 0 to 13 are RTC hardware registers. Refer to 3.8 for an explanation of their usage and setup values.

After power-up or upon system reset the Time Last Used is checksummed and if the lower byte of the sum is not 0FFh or if the battery voltage low bit is set in the RTC status register, then the values in the default column are loaded into their respective locations and a warning message is displayed on the primary display device. Those locations without defaults (marked with '--') are not initialized.

2.6 ROS Messages

The ROS outputs a number of messages during Power-Up Self Test initialisation as detailed below. The language in which these messages are displayed is dependent of the three option links connected to the three least significant bits of the system printer port status. (See Table 3.1 for the interpretation of the three link bits.)

2.6.1 Non-Fatal ROS Messages

The following messages are displayed on the primary display screen (in the default display mode as specified by the NVR ) in the situations as described. The initialisation process is allowed to complete even though some of them may represent self test failures.

Please wait

This message is displayed on the top line of the screen after Power-Up or after a Soft Reset ([Ctrl]+[Alt]+[Del]) from the keyboard. A dot is displayed after it for each major hardware self test segment completed successfully.

Amstrad PPC nnnK (Vv.i) Last used at hh:mm on dd mn yy

This message is displayed after the successful completion of all self tests, where:

nnn	= the RAM size in kilobytes.
v.i	= the ROS Version (v) and Issue (i) number.
hh:mm	= the hours (hh) and the minutes (mm) of last on time.
dd mn yy	= the day (dd), the calendar month (mn) and the year (yy) of the last date used.

Please fit new batteries

This message is displayed below the AMSTRAD PC message when it is noted that the RTC battery voltage low bit (VRT) is set (indicating that there is either no battery installed or that the battery is very near to failing).

Check keyboard and mouse

This message is displayed when the keyboard self test firmware does not respond with the test pass (0AAh).

Insert a SYSTEM disk into drive A
Then press any key

This message set is displayed when the floppy disk bootstrap is unable to successfully read the bootstrap sector from drive A after 10 retries.

Error: External ROM checksum incorrect: ROM address = nnnnnh

This message is displayed when the checksum on an external ROM is not zero (See section 2.1 - 16). The physical address of the ROM is displayed in five (nnnnn) hexadecimal digits.

2.6.2 Fatal ROS Messages

The following messages indicate that a self test segment has failed and that initialisation cannot continue. In this situation the machine must be switched off and on again in order to reinitiate operations. The display is switched to 80 column alpha mode and cleared prior to displaying any of these messages.

• Error: Faulty SYSTEM RAM
• Error: Faulty VDU RAM
• Error: Faulty interrupt controller
• Error: Faulty direct memory access controller
• Error: Faulty floppy disk controller or disk drive
• Error: Faulty interval timer
• Error: Faulty system status register
• Error: Faulty real time clock
• Error: Faulty VDU controller
• Error: Faulty system printer port
• Error: Faulty system serial port
• Error: Faulty ROS ROM checksum
• Error: Faulty memory (parity error)

When one of these failures occurs, no other testing is run since further testing may require use of the failing component. For this reason the system is placed in a non-interruptible loop. Failures of this sort are not expected to occur even intermittently. When any self test failure does occur it should be referred to a qualified Amstrad service facility for further diagnostic testing.